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Apple Watch Sport Series 2智能手表( 42毫米深空灰色铝金属表壳搭配黑色运动型表带 MP062CH/A)
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品牌：上市时间：2017年05月功能：GPS定位防水级别：生活防水表带材质：金属
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京东直接用箱子送货，里面还加满了气袋，包装满分！使用了近1个月，基本符合期望，做工精细，苹果的设计让人放心。建议想买这款的朋友首先弄清楚这款产品的定位，这个无法替代手机，想当作娱乐使用就别想了。这款的定位主要是运动场景的使用，记录运动数据，脱离iPhone跑步运动很好。
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获取手机验证码最新间谍照：今年三款iPhone一半LCD屏 5月量产-电子发烧友网触屏版
日前，投资银行加拿大皇家银行资本市场（RBC Capital）的分析师发布了一份新的报告。不出所料，该投行的分析师与其他分析师同行的意见保持一致，声称苹果在2018年秋季发布会上将会发布三款 iPhone，其中1款为 LCD 屏幕，另2款为 OLED 屏，并且不久之后这三款产品将全部投产。
根据加拿大皇家银行分析师 Amit Daryanani 的报告，iPhone除了两款 OLED 机型之外，还将有一款 6.1 英寸 LCD 全面屏的机型，同样提供基于 3D 传感器的面容 ID 功能。该分析师预计，2018 年下半 iPhone 的产量将会达到 8000 - 9000 万部，但在这其中 LCD 机型的产量将约占一半。
尽管年初诸多多消息认为今年 iPhone 8/X 这一代出货量低于预期的 1 亿部，但加拿大皇家银行认为，基于零部件供应商订单量预测结果并不准确，订单的减少主要是因为&供应链伙伴更勤于整理库存&而已。该投行接着表示，苹果仍将坚持严格的增量式成本管理模式，而此举将意味着更新一代 iPhone 可能会融入更多功能，至少面容 ID 会在新品上全线标配。
分析师 Amit Daryanani 预计，新一代 iPhone 量产计划将于5月份开始，同时也会经历常规的产能爬坡期，也就是先试产看良率再确定最终量产时间。毕竟去年 iPhone 8 也是从 5 月份开始量产，但试产 iPhone X 良率低，直到 9 月底和 10 月初才开始真正实现规模化的量产。
关于 LCD 屏 iPhone 占据 2018 年 iPhone 一半产量的说法，其实过往有不少几乎一致的分析预测。最近是 3 月份台媒 Digitime 发布的报道，声称 LCD 屏 iPhone 占据 50% 产量。再早一点是一份 IHS Markit 获取自面板上游供应链的消息，同表示 LCD 占据 2.7 亿面板订单超过一半的量。再更早一点，知名分析师郭明錤也发表过类似的言论。
Amit Daryanani 还表示，随着新 iPhone 的推出，苹果的服务业务增长速度将超过预期，但苹果智能手机和平板电脑的市场份额还会下降。不过，他认为整个 2018 财年苹果的业绩仍相当乐观，因为有新 iPhone 机型的发布，Mac 和 iPad 都会更新换代，苹果可能还会推出新的流媒体服务，或公布一条新的产品线等。
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8765432REV ECN&ECN&1DESCRIPTION OF REVISION&ECO_DESCRIPTION&1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. 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1DESCRIPTIONSCHEM,WHITE_ARROW,MLB,K18 PCBF,WHITE_ARROW,MLB,K18CRITICALCRITICAL CRITICALBOM OPTIONR&E4LABEL&BRANCHNOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&BRANCH&PAGETITLE=MLBABBREV=DRAWINGLAST_MODIFIED=Mon Feb 1 10:13:48 20101 OF 132SHEET1 OF 101876543218765U26004321U8000INTEL CPUPRAPHICS NV GT216PG 732.X GHZ ARRANDALEPG 9XDP CONNPG 25J29002 UDIMMs DDR3-MHZDIMMJ6950 PG 28,30DDDC/BATTPG 63POWER SUPPLYGPIOPG 20FDIPG 18DMIPG 18RTCPG 17 U4900TEMP SENSORU2700CLOCK CK505P8 26CLK BUFFERPG 17MiscPG 20 U6100PG 44J4500SPIPG 17SPI Boot ROMPG 56POWER PGSENSE 44JFAN CONN AND CONTROLPG 51SATA Conn HDP8 401.05V/3GHZ.INTELSATAU4900B,0 BSBADCIBEX PEAK-MPCHLPCSMCPG 44 PG 17Fan Ser PrtJ5100J4501SATA1.05V/3GHZ.PG 17CJ9000LPC Conn Port80,serialPG 46Conn ODDP8 40CU1800PWRDP OUT RGB OUTJ J J,4720DISPLAY PORT CONNPG 84CTRL0 1 2 3 4 5 6 7 8 9 10 11 12 13HDMI OUTU9600BluetoothPG 33TRACKPAD/ KEYBOARDPG 52IRPG 33CAMERAPG 33EXTERNAL USBConnectorsPG 41LVDS OUTPG 85TMDS OUTPG 18PCIPG 19 J9400BLVDS CONNPG 71PCI-EPG 19(UP TO 14 DEVICES)GMUX XP2-5DVI OUTUSBPG 19BSMBPG 17JTAGPG 17SMB CONNDIMM’sPG 47PEGPG 17PCI-E(UP TO 16 LINES)PG 17HDAPG 17U6200Audio CodecPG 57U4100U3900J3500U6500U30,AJFW643PG 37BCM5764MPG 35GB E-NETEXPRESSCARDCONNPG 34Line In AmpHEADPHONE AmpLine Out AmpPG 59Speaker AmpsPG 60SYNC_MASTER=K17_REFPAGE TITLESYNC_DATE=06/30/2009ASystem Block DiagramDRAWING NUMBER SIZEJ4000RApple Inc.E-NET ConnPG 36 PG 61 J82,&SCH_NUM& DREVISIONMini PCI-E AirPortPG 28E-NET ConnPG 39&E4LABEL&BRANCHAudio ConnsNOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&BRANCH&PAGE2 OF 132SHEET2 OF 10187654321876543SMC PWRGD NCP303LSN U5000 (PAGE 45) SMC_RESET_L21K17 POWER SYSTEM ARCHITECTUREPPDCIN_G3H_OR_PBUS_R R6905 ENABLE3.425V G3HOT SMC_PBUS_VSENSESMC AVREF SUPPLY PP3V42_G3H PP3V3_S5_AVREF_SMCVINJ6900F7040VPPBUS_G3HQ5315LT3470A U6990 (PAGE 63)VR5020 VOUT (PAGE 45)SMC_TPAD_RST_L SMC_ONOFF_LDACADAPTERF6905 6A FUSEDCIN(16.5V)R7020DINASMC_DCIN_ISENSEVINU7000VOUTPPVBAT_G3H_CHGR_REGVINISL6259HRTZ PBUS SUPPLY/ BATTERY CHARGERF7041 8A FUSEPP5V_S3_GPUVCORE VDDVOUTAU5410SMC_GPU_ISENSE GPUVCORE_PGOODVSMC_GPU_VSENSE PPVCORE_GPU PP5V_S0_CPUVTTS0 VINVOUTR7640U5001GPU VCORE ISL6263C U8900VR_ON PGOOD1.05VTPS5 CPUVTTS0_ENEN PGOODAPPCPUVTT_S0SMC_CPU_FSB_ISENSER7050AGPUVCORE_ENSMC_CPU_HI_ISENSECPUVTTS0_PGOOD(PAGE 69)SMC_BATT_ISENSE(PAGE 64)J6950(PAGE 81)R5388CPU VCORE VOUT VIN ISL9522Q7055PPVBATT_G3H_CONN(6 TO 8.4V)PPVBAT_G3H_CHGR_R2S4PAASMC_CPU_ISENSEVSMC_CPU_VSENSEPPVCORE_S0_CPUIBEX PEAK MPM_PWRBTN_LPWRBTN# SYS_RERST# RSMRST#CHGR_BGATECPUIMVP_VR_ON VR_ONU7400PGOODCPUIMVP_GOODACPRESENT(PAGE 67)PM_PCH_PWRGDPS_PWRGDPLTRST#PLT_RERST_L CPU_PWRGD PM_MEM_PWRGDCGMUXU9600 XP2-5(PAGE 86)U1800PB16B PB17A PB17B PB18A PL32APROCPWRGD DRAMPWROKEG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_ENP1V1GPU_EN P3V3GPU_EN GPUVCORE_EN P1V8_S0GPU_EN VINVLDOIN VOUT1CU5440PP5V_S3_DDRREGSMC_CPU_DDR_VSENSEU2850(PAGE 17~22)R7350SMC_DDR_ISENSEVPP1V5_S3PM_ALL_GPU_PGOODDDRREG_ENP1V1GPU_ENEN1VINPP1V1_S0GPUVOUT1S51.5VPPDDR_S3_REG PPVTT_S0_DDR_LDODDRVTT_ENA1.103V(L/H)R5413S3 0.75V VOUT2SMCU4900P60 RC SMC_PM_G2_ENDELAYP1V8FB_ENVOUT2EN2 1.8V(R/H) ISL (PAGE 85)POK1 POK2APP1V8_S0GPUSMC_GPU_1V8_ISENSECPUTPS51116 DDRREG_PGOOD U7300 PGOOD (PAGE 66) Q7860 PP5V_S0_FET P1V5DDR_EN SLG5AP020 PP1V5_S0 VOUTONSM_DRAMPWROKU1000 VCCCPUPWRGDRESET* (PAGE 9~14)PP1V2_GMUX_FETP1V1GPU_PGOOD P1V8FB_PGOOD Q7850P3V3S5_EN(PAGE 44)U7801 VINEN1P5VS0_ENVOUT1P1V2GMUX_EN PM_ALL_GPU_PGOODIBEX_PEAK_MSLP_S5#(E4) PM_SLP_S5_L Q9806 RCDELAYP5VS3_ENPP5V_S3 PP3V3_S5PP3V3_S55V 3.3V(R/H)(L/H)P3V3S5_ENVOUT2EN2P1V2ENET_ENENVINISL8009BBU7760 VOUT(PAGE 70)PP1V2_ENETU7980 ALL_SYS_PWRGDSMCPWRGD(P12)P5VS3_ENRCDELAYDDRREG_ENU1800P3V3S3_EN PM_SLP_S4_LBKLT_PLT_RST_L && LCD_BKLT_EN BKLT_EN ENATPS5 (PAGE 65) PGOOD1 PGOOD2Q7870PP3V3_S0_GPUSMC_ADAPTER_EN(P64)BRSMRST_PWRGD P1V5_EXP_S0_ENP3V3GPU_EN EN VINRSMRST_IN(P13)PM_RSMRST_L RSMRST_OUT(P15)99ms DLYVIN APP001P3V3S5_PGOOD P5VS3_PGOOD PPVOUT_S0_LCDBKLTISL8009BOUTPP1V5_EXP_S0SMC_ONOFF_LPWR_BUTTON(P90)IMVP_VR_ON PM_SYSRST_LU7710IMVP_VR_ON(P16)U9700VOUT (PAGE 87)Q7810PP3V3_S3(PAGE 70) Q7922 PP3V3_ENETSYSRST(PA2)PP3V3_S0_PWRCTL P1V8S0_PGOODPM_SLP_S5_L PM_SLP_S4_LSLP_S4_L(P94) SLP_S5_L(P95) RES*P17(BTN_OUT)PM_PWRBTN_L SMC_RESET_LSLP_S4#(H7)P3V3S3_ENQ4260 PM_SLP_S3_L SLP_S3#(P12)Q7830PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN PP3V3_S0_FET VIN P1V8_S0_EN ENP5VS3_PGOODS0PGOOD_PWROKVINLTC1872PFWBOOST VOUTPM_SLP_S3_LSLP_S3_L(P93)U7790(PAGE 17~22)SMC_ADAPTER_EN&&PM_SLP_S3_L(PAGE 70)P3V3S0_ENISL8014VOUTPP1V8_S0 P1V8S0_PGOODU7720(PAGE 70) PGOODPP3V3_S0VCCU4900 (PAGE 44)Q3810 SMC_GFX_VSENSE R7540 GFXIMVP_ISENSEVOUTR7978VPPVCORE_S0_GFXQ4291PP3V3_FW_FETPP1V5_S0ADJ1U7971RST*ISL88042IRTEZ PP1V05_S0ADJ2PM_SLP_S3_L_RVIN1.05V AUXARC DELAY RC DELAY RC DELAY RC DELAYP1V8S0_EN P5VS0_EN P1V2GMUX_EN P3V3S0_EN CPUVTTS0_EN PBUSVSENS_EN P1V5DDR_ENGFX_VR_EN VR_ONAGFXIMVP_PGOODFW_PWR_EN(PAGE 72)TRST = 200mSTPS51981SYNC_MASTER=K17_REFPAGE TITLESYNC_DATE=06/30/2009AU7500(PAGE 68) GFX_DPRSLPVR DPRSLPVRPGOODPower Block DiagramDRAWING NUMBER SIZEApple Inc.R&SCH_NUM& DREVISION&E4LABEL&BRANCHNOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&BRANCH&PAGE3 OF 132SHEET3 OF 1018765432187654321PROTO:DDCCBBASYNC_MASTER=MASTERPAGE TITLESYNC_DATE=MASTERARevision HistoryDRAWING NUMBER SIZEApple Inc.R&SCH_NUM& DREVISION&E4LABEL&BRANCHNOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&BRANCH&PAGE4 OF 132SHEET4 OF 1018765432187BOM NAME PCBA,2.0G,512SAM_VRAM,K18 PCBA,2.0G,512HYN_VRAM,K18 PCBA,2.13G,512SAM_VRAM,K18 PCBA,2.13G,512HYN_VRAM,K18 PCBA,2.4G,512SAM_VRAM,K18 PCBA,2.4G,512HYN_VRAM,K18 K18 DEVELOPMENT BOM6TABLE_BOMGROUP_HEAD5PART NUMBER ALTERNATE FOR PART NUMBER BOM OPTION43TABLE_ALT_HEAD21BOM VariantsBOM NUMBER 639-3 639-5 639-0956 BOM OPTIONSTABLE_BOMGROUP_ITEMAlternate PartsREF DES COMMENTS:TABLE_ALT_ITEMK18_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,K18_PVT,EEEE_DCJ7TABLE_BOMGROUP_ITEM138S8TABLE_BOMGROUP_ITEM138S5 152S9 333S6 152S3 333S7 128S9 128S0294ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALLMurata alt to SamsungTABLE_ALT_ITEMK18_COMMON,CPU_2_4GHZ,FB_256_HYNIX,K18_PVT,EEEE_DCJ8 K18_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJ9TABLE_BOMGROUP_ITEMDelta alt to TDK MagneticsTABLE_ALT_ITEM152S7TABLE_BOMGROUP_ITEMMAG LAYERS ALT TO CYNTECTABLE_ALT_ITEMK18_COMMON,CPU_2_53GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJC K18_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJDTABLE_BOMGROUP_ITEMMAG LAYERS ALT TO MURATATABLE_ALT_ITEM333S5TABLE_BOMGROUP_ITEMHynix 900M alt to 1000MTABLE_ALT_ITEMD639-4K18_COMMON,CPU_2_66GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJFMolex alt to FoxconnTABLE_ALT_ITEMD152S5 333S4Mag layer alt to VishayTABLE_ALT_ITEMFairchild wafer optionTABLE_ALT_ITEMSamsung I die alt to HTABLE_ALT_ITEMSanyo alt to KemetTABLE_ALT_ITEMK18 BOM GROUPSTABLE_BOMGROUP_HEAD128S0303Panasonic alt to SanyoTABLE_ALT_ITEMBOM GROUP K18_COMMON K18_COMMON1 K18_COMMON2 K18_PVT K18_PROGPARTS BOM GROUPFB_256_SAMSUNG FB_256_HYNIX FB_512_SAMSUNG FB_512_HYNIXBOM OPTIONSTABLE_BOMGROUP_ITEM337S5TABLE_BOMGROUP_ITEMA02 alt to A03 GPUTABLE_ALT_ITEMALTERNATE,COMMON,K18_COMMON1,K18_COMMON2,K18_PROGPARTS,USBHUB_2061,RDRV:8515A2,DCIBATT_3S,BCM5764M,GL137,CPUPOC_IMAX_40_50,CPUMEM_S0,SMC_EXCARD_NOT,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREMTABLE_BOMGROUP_ITEM6.3V alt to 11V SanyoGMUXPLL_3V3,GPU_SS_INT,MIKEY,GPUVID_0P90V,DPMUX_EN_PLD,DP_CA_DET_EG_PLD,DP_ESD,VFRQ_SLPS3,SMC_OSC_YES,RAIL_MONTABLE_BOMGROUP_ITEMBMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPMTABLE_BOMGROUP_ITEMGMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROGTABLE_BOMGROUP_HEADBOM OPTIONSTABLE_BOMGROUP_ITEMVRAM4,VRAM_256_SAMSUNG,FB1V55TABLE_BOMGROUP_ITEMVRAM4,VRAM_256_HYNIX,FB1V55TABLE_BOMGROUP_ITEMVRAM4,VRAM_512_SAMSUNG,FB1V35TABLE_BOMGROUP_ITEMVRAM4,VRAM_512_HYNIX,FB1V35CCBar Code Labels / EEE #’sPART NUMBER826-3 826-3 826-3QTY1 1 1 1 1 1DESCRIPTIONLBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MMREFERENCE DES[EEEE:DCJ7] [EEEE:DCJ8] [EEEE:DCJ9] [EEEE:DCJC] [EEEE:DCJD] [EEEE:DCJF]CRITICALCRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICALBOM OPTIONEEEE_DCJ7 EEEE_DCJ8 EEEE_DCJ9 EEEE_DCJC EEEE_DCJD EEEE_DCJFBModule PartsPART NUMBER337S7 337S9 337S3 341S3 338S3 335S2 341S6 336S0025QTY1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4DESCRIPTIONARD,SLBPE,PRQ,2.66G,35W,C2,3M,BGA ARD,SLBPF,PRQ,2.53G,35W,C2,3M,BGA ARD,SLBNA,PRQ,2.4G,35W,C2,4M,BGA IC,PCH,IBEX PEAK-M,SLGZS,PRQ,B3,BGA IC,GPU,NV GT216 LP++,969BGA,40NM,A03IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN IC,1MBIT,SPI FLASH,K17/K18 IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12REFERENCE DESU U U U U U U UCRITICALCRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICALBOM OPTIONCPU_2_66GHZ CPU_2_53GHZ CPU_2_4GHZBBCM5764MIC,SMC,HS8/2117,9MMX9MM,TLP IC,SMC,K18IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOPSMC_BLANK SMC_PROG BOOTROM_BLANK BOOTROM_PROGIC,EFI ROM,DEVELOPMENT,K18IR,ENCORE II, CY7C63833-LFXCIC,PSOC +W/USB,56PIN,MLF,K18 IC,XP2-5,HF,CPLD,BLANK IC,CPLD,LATTICE,132CSBGA,K18TPAD_PROG GMUX_5K_BLANK GMUX_PROG VRAM_256_SAMSUNG VRAM_256_HYNIX VRAM_512_SAMSUNG VRAM_512_HYNIXRA341S7 333S3 333S0535IC,SGRAM,GDDR3,16MX32,1000MHZ,136 FBGA U,U IC,SDRAM,GDDR3,16MX32,900MHZ,136 FBGA U,USYNC_MASTER=K17_REFPAGE TITLESYNC_DATE=05/28/2009ABOM ConfigurationDRAWING NUMBER SIZEIC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA U,U IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA U,UApple Inc.NOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&SCH_NUM& DREVISIONDevelopment BOMPART NUMBER085-1404&E4LABEL&BRANCH&BRANCH&PAGEQTY1DESCRIPTIONK18 MLB DEVELOPMENTREFERENCE DESDEVELCRITICALCRITICALBOM OPTIONDEVEL_BOM5 OF 132SHEET5 OF 101876543218J5650 (LEFT FAN CONN) FUNC_TEST 70 72 86 88 PP5V_S0 TRUE 6 7 23 42 4752 54 68 697USB PORTS PP5V_S3_RTUSB_A_F USB2_LT1_N USB2_LT1_P GND PP5V_S3_RTUSB_B_F USB_LT2_N USB_LT2_P GNDI1038 TRUE I1039 TRUE I1040 TRUE6I110343 43 99 43 995I I I4FUNC_TEST 88 I720 TRUE BKLT_EN I722 TRUE TP_ISSP_SCLK_P1_1 8 53 I724 TRUE TP_ISSP_SDATA_P1_0 8 53 87 88 I723 TRUE LCD_BKLT_PWM 20 47 I725 TRUE LPCPLUS_GPIO I726 TRUE LPCPLUS_RESET_L 27 47 87 94 LPC_AD&0..3& 17 45 47 87 94 I727 TRUE LPC_CLK33M_LPCPLUS 27 47 94 I729 TRUE LPC_FRAME_L 17 45 47 87 94 I728 TRUETRUE I732 TRUE I731 TRUE I734 TRUE I733 TRUE I735 TRUE TRUE I737 TRUE I739 TRUE I738 TRUE I740 TRUE I741 TRUE I742 TRUE I743 TRUE I744 TRUE I751 TRUE I752 TRUE TRUE I760 I756 TRUE I1292 TRUE I1288 TRUEI73032I I7621NO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUEFunctional Test Points3 TPs per FanTRUETRUE TRUEFAN_LT_PWM FAN_LT_TACH52 52J5660 (RIGHT FAN CONN)DTRUE TRUE TRUEFAN_RT_PWM FAN_RT_TACH GND52 52I1042 TRUE I1043 TRUE I1044 TRUE TRUE43 43 99 43 99I I I I5 TPs per FanJ6780 (MIC CONN)I557 I558 I559I62 63 62 63 62 63TRUE TRUE TRUEBI_MIC_N BI_MIC_SHIELD BI_MIC_PI1119J6781 & J6782 (SPEAKERS CONN)I989 I990 I992 I991 I994 I993TRUE TRUE TRUE TRUE TRUE TRUESPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N61 62 99 61 62 99 61 62 99 61 62 99 61 62 99 61 62 99CI995 I996 I997 I998 I I I I I I I I I I1018J3401 & J3402 (AIRPORT/BT/CAMERA CONN) I 94 I TRUE PCIE_AP_D2R_P 17 33 94 I TRUE PCIE_AP_D2R_N TRUE PCIE_AP_R2D_P 33 94 I 33 94 I TRUE PCIE_AP_R2D_N I1054 TRUE PCIE_CLK100M_AP_CONN_P 33 I1125 99 PCIE_CLK100M_AP_CONN_N 33 I TRUE 99 33 I TRUE AP_CLKREQ_Q_L 18 27 33 I TRUE PCIE_WAKE_L 33 I TRUE AP_RESET_CONN_L TRUE PP3V3_WLAN 33 I I1061 TRUE PP5V_S3_ALSCAMERA_F 33 J6950 (BIL CABLE CONN) I1060 TRUE SMBUS_SMC_A_S3_SDA 6 33 45 48 54 97 I1063 TRUE SMBUS_SMC_A_S3_SCL 6 33 45 48 54 97 TRUE USB_CAMERA_CONN_P 33 93 I TRUE PP5V_S3_IR_R I1064 TRUE USB_CAMERA_CONN_N 33 93 I1149 TRUE SMC_LID_R 33 99 I1066 TRUE CONN_USB2_BT_P I1151 TRUE IR_RX_OUT 33 99 I1065 TRUE CONN_USB2_BT_N I1152 TRUE SYS_LED_ANODE J3500 (SD CARD CONN) GNDTRUEIJ5713 (KEY BOARD CONN) 73 87 101 35 36 48 50 TRUE PP3V3_S3 6 7 8 17 20 31 32 33 34 53 54 55 72 TRUE PP3V42_G3H 6 7 17 21 23 43 45 46 47
64 TRUE WS_KBD1 65 66 73 53 TRUE WS_KBD2 TRUE WS_KBD3 53 53 TRUE WS_KBD4 TRUE WS_KBD5 53 53 TRUE WS_KBD6 TRUE WS_KBD7 53 TRUE WS_KBD8 53 TRUE WS_KBD9 53 53 TRUE WS_KBD10 53 TRUE WS_KBD11 WS_KBD12 TRUE 53 53 TRUE WS_KBD13 53 TRUE WS_KBD14 53 TRUE WS_KBD15_CAP 53 TRUE WS_KBD16_NUM TRUE WS_KBD17 53 TRUE WS_KBD18 53 WS_KBD19 TRUE 53 TRUE WS_KBD20 53 53 TRUE WS_KBD21 53 TRUE WS_KBD22 WS_KBD23 53 TRUE TRUE WS_KBD_ONOFF_L 53 TRUE WS_LEFT_SHIFT_KBD 53 TRUE WS_LEFT_OPTION_KBD 53 TRUE WS_CONTROL_KBD 53ICT Test PointsCPU NO_TESTsNO_TEST9NC NO_TESTsNC_SMC_FAN_3_TACH 45 46 NC_SMC_FAN_3_CTL 45 46 NC_SMC_FAN_2_TACH 45 46 NC_SMC_FAN_2_CTL 45 46 NC_FW2_TPBP 39 41 NC_FW2_TPBN 39 41 NC_FW2_TPBIAS 39 41 NC_FW2_TPAP 39 41 NC_FW2_TPAN 39 41 NC_FW0_TPBP 39 41 96 NC_FW0_TPBN 39 41 96 NC_FW0_TPAP 39 41 96 NC_ESTARLDO_EN 45 46 NC_ALS_GAIN 45 46 NC_FW643_AVREG 6 39 TRUE MAKE_BASE=TRUE NC_FW643_TDI TRUE 6 39 MAKE_BASE=TRUE NC_DP_IG_C_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLP&3..0& TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLN&3..0& TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXN TRUE MAKE_BASE=TRUE NC_DP_IG_D_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLP&3..0& TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLN&3..0& TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXN TRUE MAKE_BASE=TRUETRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUETP_CPU_RSVD&65..62& TP_CPU_RSVD&58..45& TP_CPU_RSVD&43..32&9LPC_PWRDWN_L LPC_SERIRQ PM_CLKRUN_L PM_SYSRST_L SMC_MD1 SMC_NMI SMC_ONOFF_L SMC_RESET_L SMC_RX_L18 45 47 17 45 479TP_CPU_RSVD&27..26& TP_CPU_RSVD&24..15& TP_CPU_RSVD&2..1& TP_CPU_RSVD_NCTF&8..5&9 18 45 47 18 27 45 45 47 45 47 45 46 53 45 46 47 65 43 45 46 47 18 6 45 46 47 18 6 45 46 47 18 6 45 46 47 45 46 47 18 6 45 47 18 6 43 45 46 47 20 47 57 18 6 47 18 6 47 47 18 6 47 18 6 42 18 6 9NC_TP_CPU_RSVD&65..62& TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD&58..45& TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD&43..32& 9 TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD&27..26& TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD&24..15& TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD&2..1& TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD_NCTF&8..5& TRUE MAKE_BASE=TRUE39 6 39 6I763 I764 I765 I767 I766 I769 I768 I770 I7729DI771 I774NC NO_TESTsNO_TESTNC_FW643_AVREG NC_FW643_TDI NC_DP_IG_C_HPD NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA TP_DP_IG_C_MLP&3..0& TP_DP_IG_C_MLN&3..0& NC_DP_IG_C_AUXP NC_DP_IG_C_AUXN NC_DP_IG_D_HPD NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA TP_DP_IG_D_MLP&3..0& TP_DP_IG_D_MLN&3..0& NC_DP_IG_D_AUXP NC_DP_IG_D_AUXN NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP NC_SDVO_STALLN NC_SDVO_STALLP NC_SDVO_INTN NC_SDVO_INTP NC_GPU_BUFRST_L TP_GPU_GSTATE&0& TP_GPU_GSTATE&1& TP_GPU_MIOA_D&9..0& TP_GPU_MIOA_DESMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TRST_LSMC_TX_LNC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA NC_PCH_LVDS_VBGNC_CRT_IG_BLUE TRUE MAKE_BASE=TRUE NC_CRT_IG_GREEN TRUE MAKE_BASE=TRUE NC_CRT_IG_RED TRUE MAKE_BASE=TRUE6 18 18 6 6 18 18 6 6 18 18 66 18 6 18 6 18 18 18 6 18 6 18NC_CRT_IG_DDC_CLK 6 TRUE MAKE_BASE=TRUE NC_CRT_IG_DDC_DATA TRUE MAKE_BASE=TRUE NC_CRT_IG_HSYNC TRUE MAKE_BASE=TRUE NC_CRT_IG_VSYNC TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE TRUE NC_LVDS_IG_CTRL_DATA MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUEMAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE18 6 18 18 6 18 6SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO SPI_ALT_MOSI SYS_LED_ANODE_R6 18 6 18 18 6 18 6 6 18 6 18 6 18 18 6 18 66 18 6 18 6 18 18 18 6 18 6 1817 6 42 17 6 64 17 6 42 44 42 46NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN318 6 6 17 6 17 18 6 6 17 18 6NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP NC_SDVO_STALLN NC_SDVO_STALLP NC_SDVO_INTN NC_SDVO_INTP6 18 6 18NCNO_TEST NO_TESTs19 6 19 618 6 18 66 18 6 18J9000 (LVDS CONN)TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUEBI IPP3V3_SW_LCD 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 PP3V3_S0 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 PPVOUT_S0_LCDBKLT 73 80 83 2 TP needed LVDS_DDC_CLK 83 84 LVDS_DDC_DATA 83 84 LVDS_CONN_A_DATA_P&0& 83 84 98 LVDS_CONN_A_DATA_N&0& 83 84 98 LVDS_CONN_A_DATA_P&1& 83 84 98 LVDS_CONN_A_DATA_N&1& 83 84 98 LVDS_CONN_A_DATA_P&2& 83 84 98 LVDS_CONN_A_DATA_N&2& 83 84 98 LVDS_CONN_A_CLK_F_P 83 98 LVDS_CONN_A_CLK_F_N 83 98 LVDS_CONN_B_DATA_P&0& 83 84 98 LVDS_CONN_B_DATA_N&0& 83 84 98 LVDS_CONN_B_DATA_P&1& 83 84 98 LVDS_CONN_B_DATA_N&1& 83 84 98 LVDS_CONN_B_DATA_P&2& 83 84 98 LVDS_CONN_B_DATA_N&2& 83 84 98 LVDS_CONN_B_CLK_F_P 83 98 LVDS_CONN_B_CLK_F_N 83 98 LED_RETURN_1 83 88 LED_RETURN_2 83 88 LED_RETURN_3 83 88 LED_RETURN_4 83 88 LED_RETURN_5 83 88 LED_RETURN_6 83 88 GND 4 TPs J4500 (SATA ODD CONN)I I1455TRUE TRUE TRUE TRUE TRUE TRUESD_D&7..0& SD_CMD SD_CLK SD_CD_L SD_WP GND34 34 34 34 37 34 37POWER RAILSFUNC_TEST 2 TPsTRUE PM_SLP_S3_L 18 31 45 73 85 TRUE PP0V75_S0_DDRVTT 7 28 30 31 67 6 54 TRUE PP18V5_S3 I603 TRUE PP1V05_S0 7 10 12 13 15 17 18 20 21 23 24 I604 25 26 40 70 73 86 PP1V05_S0GPU TRUE 7 74 76 79 81 86 I605 TRUE PP1V05_S5 7 17 71 I607 TRUE PP1V0_FW_FWPHY 7 39 40 I606 7 37 71 72 TRUE PP1V2_ENET I610 TRUE PP1V2_S0 7 72 87 I612 TRUE PP1V5_S3 7 28 30 31 67 72 I611 PP1V5_S3RS0 TRUE 7 13 16 31 42 72 73 99 I613 PP1V8R1V55_S0GPU_ISNS 7 8 50 56 75 76 77 78 TRUE I600 TRUE PP1V8R1V55_S0GPU_ISNS_R 7 50 86 I625 TRUE PP1V8_GPUIFPX 7 72 81 I624 TRUE PP1V8_S0 7 12 16 21 23 24 58 71 72 87 I623 TRUE PP3V3_ENET 7 27 37 73 I620 TRUE PP3V3_FW_FWPHY 7 39 40 41 I621 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 TRUE PP3V3_S0 6 7 17 18 19 20 21 23 24 25 26 I618 27 28 30 34 37 40 42 46 47 48 73 80 PP3V3_S0GPU TRUE 7 72 74 79 80 81 82 84 I617 TRUE PP3V3_S3 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 I615 55 72 73 87 101 TRUE PP3V3_S5 7 17 18 19 20 21 23 27 31 35 57 I616 66 71 72 73 83 85 99 TRUE PP3V3_S5_AVREF_SMC 45 46 I614 PP3V42_G3H TRUE 6 7 17 21 23 43 45 46 47 48 49 I627 53 64 65 66 73 TRUE PP5V_S0 6 7 23 42 47 52 54 68 69 70 72 I626 86 88 TRUE PP5V_S3 7 31 33 42 43 44 46 54 56 58 61 66 67 72 I639 82 101 TRUE PP5V_S5 7 23 66 72 I638 TRUE PPBUS_G3H 7 40 49 65 66 67 69 70 82 86 89 I637 TRUE PPDCIN_G3H 7 64 65 I636 TRUE PPVCORE_GPU 7 49 75 82 I709 PPVCORE_S0_CPU 7 12 15 49 68 I714 TRUE TRUE PPVCORE_S0_GFX 7 13 24 49 69 I 41 I1160 TRUE PPVP_FW 7 32 67 I1161 TRUE PPVTTDDR_S3I640 I60219 6 19 6 19 6 19 6 19 6 19 6TP_PCI_AD&31..0& TP_PCI_C_BE_L&3..0& NC_PCI_GNT3_L NC_PCI_GNT2_L NC_PCI_GNT1_L NC_PCI_GNT0_L NC_PCI_PAR NC_PCI_RESET_L NC_PCI_PME_L NC_PCI_CLK33M_OUT3 NC_PCH_NV_RCOMP TP_NV_DQ&15..0& TP_NV_DQS&1..0& TP_NV_CE_L&3..0&19 619 6 19 6 19 6J5800 (IPD FLEX CONN)I1086 TRUE I1273 TRUE I1089 TRUE I1088 TRUE I1090 TRUEI1464PP18V5_S3NC_NV_ALE NC_NV_CLE NC_NV_RB_L TP_NV_WR_RE_L&1..0& TP_NV_WE_CK_L&1..0& NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_C_D2RN NC_SATA_C_D2RP NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_SSD2_D2RN NC_SATA_SSD2_D2RP NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CP6 5417 6 17 6 17 6 17 6 20 6 20 6 20 6 20 6 53 6 17 6 17 6 17 6 17 6 17 6 17 6 17 6 17 6 17 6 17 6 17 6 17 6I I I I I3 TPsI1024 TRUE I1026 TRUE I ITRUE TRUE TRUE TRUE TRUEPP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N GND42 56 42 45 42 93 42 93 42 93 42 93TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUEZ2_CS_L 53 54 Z2_DEBUG3 53 54 Z2_MISO 53 54 Z2_BOOST_EN 54 Z2_SCLK 53 54 Z2_CLKIN 53 54 Z2_KEY_ACT_L 53 54 Z2_RESET 53 54 PSOC_F_CS_L 53 54 PICKB_L 53 54 PSOC_MISO 53 54 PSOC_MOSI 53 54 PSOC_SCLK 53 54 SMBUS_SMC_A_S3_SCL 6 33 SMBUS_SMC_A_S3_SDA 6 3345 48 54 97 45 48 54 97J6900 (DC POWER CONN) I1131 TRUE ADAPTER_SENSE I1132 TRUE PP18V5_DCIN_FUSE 5 TPsTRUE64 64GNDTRUE 18 6 MAKE_BASE=TRUE 19 TRUE 18 6 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 74 6 TRUE 80 79 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 80 TRUE MAKE_BASE=TRUE 80 79 TRUE 80 79 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 19 TRUE MAKE_BASE=TRUE NC_PCH_NV_RCOMP TRUE 6 19 MAKE_BASE=TRUE 6 NC_NV_DQ&15..0& 19 TRUE MAKE_BASE=TRUE 93 18 8 NC_NV_DQS&1..0& TRUE 19 MAKE_BASE=TRUE 93 18 8 NC_NV_CE_L&3..0& TRUE 19 18 8 MAKE_BASE=TRUE NC_NV_ALE TRUE 6 19 MAKE_BASE=TRUE NC_NV_CLE TRUE 6 19 MAKE_BASE=TRUE NC_NV_RB_L TRUE 6 19 20 MAKE_BASE=TRUE NC_NV_WR_RE_L&1..0& 19 20 TRUE MAKE_BASE=TRUE NC_NV_WE_CK_L&1..0& 19 20 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4N 6 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4P 6 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5N 6 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5P 6 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6N 6 2020 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6P 6 2020 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7N 6 2020 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7P 6 2020 TRUE MAKE_BASE=TRUE 20 NC_PSOC_P1_3 TRUE 6 53 MAKE_BASE=TRUE 20 NC_SATA_C_D2RN 6 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_C_D2RP 6 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_C_R2D_CN 6 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_C_R2D_CP 6 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_D2RN 6 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_D2RP 6 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_R2D_CN 6 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_R2D_CP 6 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_D2RN 6 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_D2RP 6 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_R2D_CN 6 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_R2D_CP 6 17 TRUE MAKE_BASE=TRUE 20NC_PCI_AD&31..0& 19 NC_PCI_C_BE_L&3..0& NC_PCI_GNT3_L 6 19 NC_PCI_GNT2_L 6 19 NC_PCI_GNT1_L 6 19 NC_PCI_GNT0_L 6 19 NC_PCI_PAR 6 19 NC_PCI_RESET_L 6 19 NC_PCI_PME_L 6 19 NC_PCI_CLK33M_OUT3 66 18 6 18CNC_GPU_BUFRST_L 6 74 TRUE MAKE_BASE=TRUE NC_GPU_GSTATE&0& TRUE MAKE_BASE=TRUE NC_GPU_GSTATE&1& TRUE MAKE_BASE=TRUE NC_GPU_MIOA_D&9..0& TRUE MAKE_BASE=TRUE NC_GPU_MIOA_DE TRUE MAKE_BASE=TRUE NC_LVDS_EG_BKL_PWM TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP TRUE MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE NC_SMC_BS_ALRT_L TRUE MAKE_BASE=TRUE NC_PCH_SST TRUE MAKE_BASE=TRUE NC_PCH_NC1 TRUE MAKE_BASE=TRUE NC_PCH_NC2 TRUE MAKE_BASE=TRUE NC_PCH_NC3 TRUE MAKE_BASE=TRUE NC_PCH_NC4 TRUE MAKE_BASE=TRUE NC_PCH_NC5 TRUE MAKE_BASE=TRUE NC_PCH_TP19 TRUE MAKE_BASE=TRUE NC_PCH_TP18 TRUE MAKE_BASE=TRUE NC_PCH_TP17 TRUE MAKE_BASE=TRUE NC_PCH_TP16 TRUE MAKE_BASE=TRUE NC_PCH_TP15 TRUE MAKE_BASE=TRUE NC_PCH_TP14 TRUE MAKE_BASE=TRUE NC_PCH_TP13 TRUE MAKE_BASE=TRUE NC_PCH_TP12 TRUE MAKE_BASE=TRUE NC_PCH_TP11 TRUE MAKE_BASE=TRUE NC_PCH_TP10 TRUE MAKE_BASE=TRUE NC_PCH_TP9 TRUE MAKE_BASE=TRUE NC_PCH_TP8 TRUE MAKE_BASE=TRUE NC_PCH_TP7 TRUE MAKE_BASE=TRUE NC_PCH_TP6 TRUE MAKE_BASE=TRUE NC_PCH_TP5 TRUE MAKE_BASE=TRUE NC_PCH_TP4 TRUE MAKE_BASE=TRUE NC_PCH_TP3 TRUE MAKE_BASE=TRUE NC_PCH_TP2 TRUE MAKE_BASE=TRUE NC_PCH_TP1 TRUE MAKE_BASE=TRUEI I I INC_LVDS_EG_BKL_PWM TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM66NC_SMC_BS_ALRT_L NC_PCH_SST NC_PCH_NC1 NC_PCH_NC2 NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18 NC_PCH_TP17 NC_PCH_TP16 NC_PCH_TP15 NC_PCH_TP14 NC_PCH_TP13 NC_PCH_TP12 NC_PCH_TP11 NC_PCH_TP10 NC_PCH_TP9 NC_PCH_TP8 NC_PCH_TP7 NC_PCH_TP6 NC_PCH_TP5 NC_PCH_TP4 NC_PCH_TP3 NC_PCH_TP2 NC_PCH_TP1TRUE TRUE TRUE TRUE TRUE TRUE TRUE66 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 66 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20 6 20BJ4501 (SATA HDD CONN)I1032 TRUE I1031 TRUE I1033 TRUE I1035 TRUE I1034 TRUEPP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P GND42 42 93 42 93 42 93 42 93J6950 (MAIN BATT CONN) I1134 TRUE PPVBAT_G3H_CONN I1136 TRUE SMBUS_SMC_BSA_SCL I1135 TRUE SMBUS_SMC_BSA_SDA I1137 TRUE NC_SMC_BS_ALRT_LTRUE46 45 64 65 6 45 48 64 65 97 6 45 48 64 65 97 17 6 6 17 6 17 6TP_SMC_P41NC_SMC_P41 TRUE MAKE_BASE=TRUEI I1438NC NO_TESTs NO_TESTNC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN NC_PCIE_PE5_R2D_CP NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RP NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CP NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN NC_PCIE_PE7_R2D_CP NC_PCIE_PE8_D2RN NC_PCIE_PE8_D2RP NC_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CPTRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUETRUEGND17 6NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN NC_PCIE_PE5_R2D_CP NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RP NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CP NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN NC_PCIE_PE7_R2D_CP NC_PCIE_PE8_D2RN NC_PCIE_PE8_D2RP NC_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CPI14396 17I14406 17I14416 17I14426 17PCH_VSS_NCTF&1& 20 94 PCH_VSS_NCTF&2& 20 94 PCH_VSS_NCTF&5& 20 94 PCH_VSS_NCTF&7& PCH_VSS_NCTF&9& 20 94 PCH_VSS_NCTF&11& 20 94 PCH_VSS_NCTF&12& 20 94TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUEPCH_VSS_NCTF&15& PCH_VSS_NCTF&17& PCH_VSS_NCTF&19& PCH_VSS_NCTF&19& PCH_VSS_NCTF&21& PCH_VSS_NCTF&25& PCH_VSS_NCTF&27& PCH_VSS_NCTF&29&20 94 20 94 6 20 94 6 20 94 20 94 20 94 20 94 20 94A17 66 17 6 17 6 17 6 17I1145 TRUE I1146 TRUEJ5815 (KBD BACKLIGHT CONN) KBDLED_ANODE 54 SMC_KDBLED_PRESENT_L 54 GNDI1140 TRUE I I1143TRUEJ6995 (BAT LED CONN) PP3V42_G3H TRUE SMBUS_SMC_BSA_SDA TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_LTRUE17 6 73 64 65 66 17 6 48 49 53 6 7 17 21 23 43 45 46 47 17 6 6 45 48 64 65 97 6 45 48 64 17 6 65 97 45 46 64 17 6 17 6SYNC_MASTER=MASTERPAGE TITLESYNC_DATE=MASTERAFunctional / ICT TestDRAWING NUMBER SIZE6 17 6 17 6 17 6 17 17 6 17 6 17 6 6 17 6 17 6 17 6 17 17 6 17 6Apple Inc.NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP NC_CLINK_CLK 6 17 TRUE MAKE_BASE=TRUE NC_CLINK_DATA 6 17 TRUE MAKE_BASE=TRUE NC_CLINK_RESET_L 6 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBN TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBP TRUE MAKE_BASE=TRUER&SCH_NUM& DREVISIONFUNC_TESTTRUE&E4LABEL&BRANCHGNDTRUE 6 TPsGND17 6NOTICE OF PROPRIETARY PROPERTY:17 6 17 6 1717 6GND17 6 17 6 17 6THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&BRANCH&PAGE7 OF 132SHEET6 OF 10187654321889 86 82 66 65 49 40 7 6 70 69 677&G3Hot& (Always-Present) RailsPPBUS_G3HMIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE99 85 83 20 19 18 17 7 6 73 72 71 66 57 35 31 27 23 2163.3V RailsPP3V3_S5 PP3V3_S5MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE56 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 994341 40 7 62&FW& (FireWire) RailsPPVP_FW PPVP_FWMIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.8V MAKE_BASE=TRUE16 7 40 411.8V/1.5V/1.2V/1.05V Rails87 72 71 58 24 23 21 73 83 85 99 16 12 7 6 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 57 66 71 72 73 83 85 99 99 6 7 17 18 19 20 21 23 27 31 57 66 71 72 73 83 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 35 35 40 39 7 6 35 85PPBUS_G3HD68 49 7PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_CPU_IMVP_ISNS PPBUS_CPU_IMVP_ISNSMIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 6 7 40 49 65 66 67 69 70 82 86 89 7 49 68PPBUS_CPU_IMVP_ISNS65 64 7 67 49 68PPDCIN_G3HPPDCIN_G3HMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE6 7 64 65PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5PP1V8_S0 2A max supplyPP1V8_S0MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE6 7 12 16 21 23 24 58 71 72 87PPVP_FW PPVP_FW6 7 12 16 21 23 24 58 71 72 87 6 7 12 16 21 23 24 58 71 72 87 41 40 39 7 6 6 7 12 16 21 23 24 58 71 72 87 6 7 12 16 21 23 24 58 71 72 87 6 7 12 16 21 23 24 58 71 72 87 6 7 12 16 21 23 24 58 71 72 87 6 7 12 16 21 23 24 58 71 72 876 7 40 41 6 7 40 41PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0PP3V3_FW_FWPHYPP3V3_FW_FWPHYMIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE6 7 39 40 41PP3V3_FW_FWPHY PP3V3_FW_FWPHY PP1V0_FW_FWPHYMIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE6 7 39 40 41 6 7 39 40 41DPP1V0_FW_FWPHY6 7 39 40PP1V5_S3PP1V5_S3MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE6 7 28 30 31 67 726 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 6 7 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99PP1V0_FW_FWPHY6 7 28 30 31 67 72 6 7 28 30 31 67 72 84 82 81 80 79 74 72 7 6 6 7 28 30 31 67 72 6 7 28 30 31 67 72 6 7 28 30 31 67 726 7 39 40PPDCIN_G3H73 53 49 48 43 23 21 17 7 6 47 46 45 66 65 646 7 64 65PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3&GPU& RailsPP3V3_S0GPU PP3V3_S0GPUMIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE6 7 72 74 79 80 81 82 84PP3V42_G3HPP3V42_G3HMIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 53 VOLTAGE=3.42V MAKE_BASE=TRUE6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 50 48 36 35 34 33 32 31 20 17 8 7 6 101 87 73 72 55 54PP3V3_S3PP3V3_S3MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101CPP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73 6 7 17 21 23 43 45 46 47 48 49 53 64 65 66 73PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP1V8_GPUIFPX PP1V8_GPUIFPXMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.8V MAKE_BASE=TRUE6 7 72 74 79 80 81 82 84 6 7 72 74 79 80 81 82 84 6 7 72 74 79 80 81 82 84 6 7 72 74 79 80 81 82 84 6 7 72 74 79 80 81 82 84PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S0MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 99 73 72 42 31 16 13 7 6 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 6 7 8 55 72 6 7 8 35 36 31 32 101 53 31 32 67 32 6 7 8 17 20 31 32 55 72 73 87 101 17 73 17 48 20 87 20 50 33 34 35 36 48 50 53 54 54 55 72 73 87 101 33 34 7 6 33 34 35 36 48 50 53 54PP1V5_S3RS0PP1V5_S3RS0MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE81 72 7 6 6 7 13 16 31 42 72 73 996 7 72 81PP1V5_S3RS0 PP1V5_S3RS0 PP1V5_S3RS0 PP1V5_S3RS0PP1V8_GPUIFPX6 7 13 16 31 42 72 73 99 6 7 13 16 31 42 72 73 99 78 77 76 75 56 50 8 7 6 6 7 13 16 31 42 72 73 99 6 7 13 16 31 42 72 73 996 7 72 81PP1V8R1V55_S0GPU_ISNSPP1V8R1V55_S0GPU_ISNSMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE6 7 8 50 56 75 76 77 78PPVTTDDR_S3PPVTTDDR_S3MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUEPP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS6 7 32 67 86 50 7 66 7 8 50 56 75 76 77 78 6 7 8 50 56 75 76 77 78 6 7 8 50 56 75 76 77 78 6 7 8 50 56 75 76 77 78C5V Rails72 66 23 7 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52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99PP5V_S5 PP5V_S5 PP5V_S572 67 66 61 58 42 33 31 7 6 56 54 46 44 43 101 82PP5V_S3PP5V_S3MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101BPP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S06 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 72 82 101 6 7 31 33 72 82 101 6 7 31 33 72 82 101 6 7 31 33 72 82 101 42 43 44 46 54 56 58 61 66 67 42 43 44 46 54 56 58 61 66 67 42 43 44 46 54 56 58 61 66 67 42 43 44 46 54 56 58 61 66 676 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 6 7 31 33 42 43 44 46 54 56 58 61 66 67 72 82 10188 86 72 47 42 23 7 6 70 69 68 54 52PP5V_S0MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE6 7 23 42 47 52 54 68 69 70 72 86 88PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S06 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88 6 7 23 42 47 52 54 68 69 70 72 86 88APP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT6 7 86 81 79 76 74 7 6 28 30 31 67 6 7 28 30 31 67 6 7 28 30 31 676 7 74 76 79 81 8650 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 6 27 28 7 17 18 19 20 21 23 24 25 26 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 87 72 7 6 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 6 27 28 7 17 18 19 20 21 23 24 25 26
40 42 46 47 48 50
58 62 63 68 69 72
84 85 87 88 99 28 6 7 17 18 19 20 21 23 24 25 26 27 71 17 7 6 30 34 37 40 46 47 48 50 51 52 54 58 62 69 68 69 72 73 80 83 84 85 87 996 7 17 18 19 20 21 23 24 47 25
30 34 37 40 42 46
52 54 58 62 63 68 6 72 73 80 83 84 85 87 88 99 7 18 19 20 21 23 24 25 26 27 28 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 21 20 18 17 15 13 12 10 7 6 86 73 70 40 26 25 24 23PP1V2_S0PP1V2_S0MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.09 MM VOLTAGE=1.2V MAKE_BASE=TRUE6 7 72 87PP1V2_S0 PP1V05_S5MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE6 7 72 87PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PPVCORE_GPU PPVCORE_GPUMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE6 7 74 76 79 81 86 6 7 74 76 79 81 86 6 7 74 76 79 81 86 6 7 74 76 79 81 86 6 7 74 76 79 81 86 6 7 74 76 79 81 86 6 7 74 76 79 81 86 6 7 74 76 79 81 86 6 7 74 76 79 81 86PP1V05_S56 7 17 71 82 75 49 7 66 7 49 75 82PP1V05_S5 PP1V05_S0MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE6 7 17 71PPVCORE_GPU6 7 49 75 82PP1V05_S0 ? mAB6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 23 24 25 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 69 49 24 13 7 6 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 6 7 10 12 13 15 17 18 20 21 16 12 7 23 24 25 266 40 70 73 86 7
15 17 18 20 21 23 6 24 25 26 40 70 73 86 26 40 7 12 13 15 17 18 20 21 23 24 25 706 73 86 7
13 15 16 12 7 7 17 18 20 21 23 24 25 26
86 13 40 70 73 86 15 17 18 20 21 23 24 25 26 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 24 13 7 6 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 8650 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 6 7 17 18 19 20 21 23 24 25 26 30 34 37 40 42 46 47 48 50
58 62 63 68 69 72
84 85 87 88 99 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 51 52 54 58 62 63 68 69 72 73 83 84 85 87 88 9950 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 6 27 28 197 17 18 19 20 21 23 24 25 26
40 42 46 47 48 50 6 51 52 54 58 62 63 68 69 72 7 73 80 83 84 85 87 88 99 18 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 6 27 28 197 17 18 19 20 21 23 24 25 26
40 42 46 47 48 50 6 51 52 54 58 62 63 68 69 72 7 73 80 83 84 85 87 88 99 18 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 6 197 17 18 19 20 21 23 24 25 26
40 42 46 47 48 50 6 51 52 54 58 62 63 68 69 72 7 73 80 83 84 85 87 88 99 18 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 73 37 27 7 6 50 51 52 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 6 7 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 58 62 63 68 69 72 73 80 83 84 28 30 34 37 40 42 46 47 48 50 6 7 17 18 19 20 21 23 24 25 26 27 72 71 37 7 6 51 52 54 85 87 88 99PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0Chipset &VCore& RailsPPVCORE_S0_CPUMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE6 7 12 15 49 68PPVCORE_S0_CPUPPVCORE_S0_CPU PPVCORE_S0_GFXMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE6 7 12 15 49 68PPVCORE_S0_GFX6 7 13 24 49 69PPVCORE_S0_GFX PPVCORE_S0_CPU_VCAP0MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE6 7 13 24 49 69PPVCORE_S0_CPU_VCAP07 12 16PPVCORE_S0_CPU_VCAP1PPVCORE_S0_CPU_VCAP1MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE7 12 16PPVCORE_S0_CPU_VCAP2PPVCORE_S0_CPU_VCAP2MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE7 13 24ENET RailsPP3V3_ENETMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE6 7 27 37 73PP3V3_ENETSYNC_MASTER=MASTERPAGE TITLESYNC_DATE=MASTERAPP3V3_ENET PP1V2_ENETMIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE6 7 27 37 73Power AliasesDRAWING NUMBER SIZEPP1V2_ENET6 7 37 71 72 RApple Inc.NOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&SCH_NUM& DREVISION&E4LABEL&BRANCHPP1V2_ENET PP1V2_ENET6 7 37 71 72 6 7 37 71 72&BRANCH&PAGE8 OF 132SHEET7 OF 101876543218STDOFF-4.5OD.98H-1.1-3.48-TH17ZT0981STDOFF-4.5OD.98H-1.1-3.48-TH16Fan Holes ZT0930STDOFF-4.5OD.98H-1.1-3.48-TH1543CPU signals CPU_VID&0..6&MAKE_BASE=TRUE21ZT0984 Thermal Module Holes ZT0987STDOFF-4.5OD.98H-1.1-3.48-TH191 15 12CPUIMVP_VID&0..6& GFXIMVP_VID&0..6& MEMVTT_EN6891 12 8TP_CPU_VTT_SELECTMAKE_BASE=TRUETP_CPU_VTT_SELECT8 12 91ZT0985STDOFF-4.5OD.98H-1.1-3.48-TH1ZT0988STDOFF-4.5OD.98H-1.1-3.48-TH191 13 67 31 8GFX_VID&0..6&MAKE_BASE=TRUE69MEMVTT_ENMAKE_BASE=TRUE8 31 67ZT0980STDOFF-4.5OD.98H-1.1-3.48-TH1ZT0986STDOFF-4.5OD.98H-1.1-3.48-TH1ZT0989STDOFF-4.5OD.98H-1.1-3.48-TH191 74 9GPU signals PEG_D2R_P&15..0&MAKE_BASE=TRUE=PEG_D2R_P&0..15& =PEG_D2R_N&0..15& =PEG_R2D_C_P&0..15& =PEG_R2D_C_N&0..15&9 9DZT09153R2P51ZT0991STDOFF-4.5OD.98H-1.1-3.48-TH191 74PEG_D2R_N&15..0&MAKE_BASE=TRUED91 74 9PEG_R2D_C_P&15..0&MAKE_BASE=TRUE91 74PEG_R2D_C_N&15..0&MAKE_BASE=TRUEFrame HolesGND** PEG LANES REVERSED. ARD STRAP REQ’D. **GMUX ALIASESZT09403R2P51Left Speaker Holes87 86 82 73 8R09028 73 82 86 87 91 25 9PM_ALL_GPU_PGOODMAKE_BASE=TRUEPM_ALL_GPU_PGOODCPU_CFG&3&13.0K 25% 1/16W MF-LF 40293 18 8 6TP_LVDS_IG_B_CLKPMAKE_BASE=TRUETP_LVDS_IG_B_CLKP TP_LVDS_IG_B_CLKN TP_LVDS_IG_BKL_PWM NC_GPU_XTALOUT8 796 8 18 93GNDZT0934STDOFF-4.0OD3.0H-TH187 8ZT0950 TH1 GND SL-3.1X2.7-6CIR-NSPTP_LVDS_MUX_SEL_EGMAKE_BASE=TRUE87 74 8TP_LVDS_MUX_SEL_EG EG_RESET_L LVDS_IG_BKL_ON8 74 8793 18 8 6TP_LVDS_IG_B_CLKNMAKE_BASE=TRUE6 8 18 938 87EG_RESET_LMAKE_BASE=TRUE18 8 6TP_LVDS_IG_BKL_PWMMAKE_BASE=TRUE6 8 18ZT09603R2P51ZT0935STDOFF-4.0OD3.0H-TH187 18 8LVDS_IG_BKL_ONMAKE_BASE=TRUE8 18 87 79 8NC_GPU_XTALOUT87 18 8LVDS_IG_PANEL_PWRMAKE_BASE=TRUE89 87 8LVDS_IG_PANEL_PWR LCD_BKLT_EN8 87 898 18 87MAKE_BASE=TRUE NO_TEST=TRUE93 18 8NC_LVDS_IG_A_DATAP&3&MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_IG_A_DATAP&3& NC_LVDS_IG_A_DATAN&3& NC_LVDS_IG_B_DATAP&3& NC_LVDS_IG_B_DATAN&3&8 18 93GNDLCD_BKLT_ENMAKE_BASE=TRUE93 18 8 93 84NC_LVDS_IG_A_DATAN&3&MAKE_BASE=TRUE NO_TEST=TRUE8 18 93ZT09903R2P51DP_IG_ML_P&3..0&MAKE_BASE=TRUEDP_IG_B_ML_P&3..0& DP_IG_B_ML_N&3..0& DP_IG_AUX_CH_P DP_IG_AUX_CH_N DP_IG_DDC_CLK DP_IG_DDC_DATA DP_IG_HPD18GND87 74 893 84DP_IG_ML_N&3..0&MAKE_BASE=TRUE1893 18 8NC_LVDS_IG_B_DATAP&3&MAKE_BASE=TRUE NO_TEST=TRUE8 18 93PEX_CLKREQ_LMAKE_BASE=TRUEPEX_CLKREQ_L PEG_CLKREQ_L PM_ENET_EN8 74 87 93 84 18 8 8 17 87 93 84 18 8DP_IG_AUX_CH_PMAKE_BASE=TRUE87 17 8PEG_CLKREQ_LMAKE_BASE=TRUE8 18 84 9393 18 8NC_LVDS_IG_B_DATAN&3&MAKE_BASE=TRUE NO_TEST=TRUE8 18 93DP_IG_AUX_CH_NMAKE_BASE=TRUE8 18 84 93Keyboard / IPD Conn Protect73 71 8PM_ENET_ENMAKE_BASE=TRUE8 71 7384 80 18 8DP_IG_DDC_CLKMAKE_BASE=TRUE35 8 8 18 80 84 36 8 8 18 80 84NC_USB_HUB1_OCS4MAKE_BASE=TRUENC_USB_HUB1_OCS4 NC_USB_HUB2_OCS3 USB_SDCARD_P USB_SDCARD_N8 35CSM 1ZT0952Tall EMI pogo pinsSH09022.0DIA-TALL-EMI-MLB-M97-M984.0OD1.85H-M1.6X0.35184 80 18 8DP_IG_DDC_DATAMAKE_BASE=TRUENC_USB_HUB2_OCS3MAKE_BASE=TRUE8 36C84 18 8DP_IG_HPDMAKE_BASE=TRUE8 18 8493 36 34 8USB_SDCARD_PMAKE_BASE=TRUE8 34 36 93ZT095340 20 8FW_PLUG_DET_LMAKE_BASE=TRUEFW_PLUG_DET_L FW643_WAKE_L TP_SMC_EXCARD_PWR_EN NC_SATA_EXTA_D2R_N NC_SATA_EXTA_D2R_P NC_SATA_EXTA_R2D_C_N NC_SATA_EXTA_R2D_C_P NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P8 20 4093 36 34 8USB_SDCARD_NMAKE_BASE=TRUE8 34 36 93SH09002.0DIA-TALL-EMI-MLB-M97-M98SM 14.0OD1.85H-M1.6X0.35140 39 8 45 8FW643_WAKE_LMAKE_BASE=TRUE8 39 4054 53 50 48 36 35 34 33 32 31 20 17 7 6 101 87 73 72 55 8 45PP3V3_S3TP_SMC_EXCARD_PWR_ENMAKE_BASE=TRUER0903110K5% 1/16W MF-LF 402 21R090410K5% 1/16W MF-LFSH09032.0DIA-TALL-EMI-MLB-M97-M98SM 117 8NC_SATA_EXTA_D2R_NMAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUESH09162.0DIA-TALL-EMI-MLB-M97-M98SM 1NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE8 1717 8NC_SATA_EXTA_D2R_P8 172 40217 8NC_SATA_EXTA_R2D_C_N NC_SATA_EXTA_R2D_C_P NC_PCIE_EXCARD_D2R_N NC_PCIE_EXCARD_D2R_P8 17USB_EXTC_N USB_EXTC_P35 93 35 93SH09042.0DIA-TALL-EMI-MLB-M97-M98SM117 88 1717 88 1717 88 1717 8NC_PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_P8 1717 88 1794 17 8NC_PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_P8 17 94 78 77 76 75 56 50 7 6 8 17 941 PP1V8R1V55_S0GPU_ISNS 10R09002GPU_FB_A_VREF_DIVMAKE_BASE=TRUE8 32 7794 17 8BShort (IO Row) EMI pogo pins SHDIA-SHORT-EMI-MLB-M97-M98 SH0910 SM1.4DIA-SHORT-EMI-MLB-M97-M98SM 1 11% 1/16W MF-LF 402GPU_FB_A_VREF_DIV GPU_FB_B_VREF_DIVMAKE_BASE=TRUE8 32 7753 8 6TP_ISSP_SCLK_P1_1MAKE_BASE=TRUETP_ISSP_SCLK_P1_1 TP_ISSP_SDATA_P1_06 8 53R090111053 8 6TP_ISSP_SDATA_P1_0MAKE_BASE=TRUE28 32 786 8 53SH09131.4DIA-SHORT-EMI-MLB-M97-M98SM 1SH09121.4DIA-SHORT-EMI-MLB-M97-M98SM 1GND GND GND GND GND1% 1/16W MF-LF 402BGPU_FB_B_VREF_DIV8 32 78SH09171.4DIA-SHORT-EMI-MLB-M97-M98SM 1SH09011.4DIA-SHORT-EMI-MLB-M97-M98SM 1Digital GroundSH09141.4DIA-SHORT-EMI-MLB-M97-M98SM1GNDMIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.095 mm VOLTAGE=0V62GND_CHASSIS_AUDIO_JACKASYNC_MASTER=K17_REFPAGE TITLESYNC_DATE=06/11/2009ASignal AliasesDRAWING NUMBER SIZEApple Inc.R&SCH_NUM& DREVISION&E4LABEL&BRANCHNOTICE OF PROPRIETARY PROPERTY:THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED&BRANCH&PAGE9 OF 132SHEET8 OF 1018765432187OMIT6543OMIT21U1000ARRANDALEBGA(SYM 1 OF 11)91 18 91 18 91 18 91 18U1000ARRANDALEBGA(SYM 5 OF 11) PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5* PEG_RX6* PEG_RX7* PEG_RX8* PEG_RX9* PEG_RX10* PEG_RX11* PEG_RX12* PEG_RX13* PEG_RX14* PEG_RX15* PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8* PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15* PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 B12 A13 D12 B11 G40 G38 H34 P34 G28 H25 H24 D29 B26 D26 B23 D22 A20 D19 A17 B14 F40 J38 G34 M34 J28 G25 K24 B28 A27 B25 A24 B21 B19 B18 B16 D15 N40 L38 M32 D40 A38 G32 B33 B35 L30 A31 B32 L28 N26 M24 G21 J20 L40 N38 N32 B39 B37 H32 A34 D36 J30 B30 D33 N28 M25 N24 F21 L2091IN IN IN IN IN IN IN INDMI_S2N_N&0& DMI_S2N_N&1& DMI_S2N_N&2& DMI_S2N_N&3& DMI_S2N_P&0& DMI_S2N_P&1& DMI_S2N_P&2& DMI_S2N_P&3& DMI_N2S_N&0& DMI_N2S_N&1& DMI_N2S_N&2& DMI_N2S_N&3& DMI_N2S_P&0& DMI_N2S_P&1& DMI_N2S_P&2& DMI_N2S_P&3&F7 J8 K8 J4 F9 J6 K9 J2 H17 K15 J13 F10 G17 M15 G13 J11DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3* DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3* DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3CPU_PEG_COMPRSVD32 W66 RSVD33 W64 RSVD34 AC69 RSVD35 AC71IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 91 25 91 25 91 25NC_TP_CPU_RSVD&32& NC_TP_CPU_RSVD&33& NC_TP_CPU_RSVD&34& NC_TP_CPU_RSVD&35& NC_TP_CPU_RSVD&36& NC_TP_CPU_RSVD&37& NC_TP_CPU_RSVD&38& NC_TP_CPU_RSVD&39& NC_TP_CPU_RSVD&40& NC_TP_CPU_RSVD&41& NC_TP_CPU_RSVD&42& NC_TP_CPU_RSVD&43& TP_CPU_RSVD&45& TP_CPU_RSVD&46& TP_CPU_RSVD&47& TP_CPU_RSVD&48& TP_CPU_RSVD&49& TP_CPU_RSVD&50& TP_CPU_RSVD&51& TP_CPU_RSVD&52& TP_CPU_RSVD&53& TP_CPU_RSVD&54& TP_CPU_RSVD&55& TP_CPU_RSVD&56& TP_CPU_RSVD&57& TP_CPU_RSVD&58& TP_CPU_RSVD&2& TP_CPU_RSVD&1& CPU_THERMD_P CPU_THERMD_N TP_CPU_RSVD&64& TP_CPU_RSVD&65&6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 66 691CPU_PEG_RBIAS =PEG_D2R_N&0& =PEG_D2R_N&1& =PEG_D2R_N&2& =PEG_D2R_N&3& =PEG_D2R_N&4& =PEG_D2R_N&5& =PEG_D2R_N&6& =PEG_D2R_N&7& =PEG_D2R_N&8& =PEG_D2R_N&9& =PEG_D2R_N&10& =PEG_D2R_N&11& =PEG_D2R_N&12& =PEG_D2R_N&13& =PEG_D2R_N&14& =PEG_D2R_N&15& PEG_D2R_P&15& PEG_D2R_P&14& PEG_D2R_P&13& PEG_D2R_P&12& PEG_D2R_P&11& PEG_D2R_P&10& PEG_D2R_P&9& PEG_D2R_P&8& PEG_D2R_P&7& PEG_D2R_P&6& PEG_D2R_P&5& PEG_D2R_P&4& PEG_D2R_P&3& PEG_D2R_P&2& PEG_D2R_P&1& PEG_D2R_P&0& =PEG_R2D_C_N&0& =PEG_R2D_C_N&1& =PEG_R2D_C_N&2& =PEG_R2D_C_N&3& =PEG_R2D_C_N&4& =PEG_R2D_C_N&5& =PEG_R2D_C_N&6& =PEG_R2D_C_N&7& =PEG_R2D_C_N&8& =PEG_R2D_C_N&9& =PEG_R2D_C_N&10& =PEG_R2D_C_N&11& =PEG_R2D_C_N&12& =PEG_R2D_C_N&13& =PEG_R2D_C_N&14& =PEG_R2D_C_N&15& PEG_R2D_C_P&15& PEG_R2D_C_P&14& PEG_R2D_C_P&13& PEG_R2D_C_P&12& PEG_R2D_C_P&11& PEG_R2D_C_P&10& PEG_R2D_C_P&9& PEG_R2D_C_P&8& PEG_R2D_C_P&7& PEG_R2D_C_P&6& PEG_R2D_C_P&5& PEG_R2D_C_P&4& PEG_R2D_C_P&3& PEG_R2D_C_P&2& PEG_R2D_C_P&1& PEG_R2D_C_P&0&6 6DD91 18 91 18 91 18 91 18R101217501% 1/16W MF-LF 402 21R101049.9RSVD36 AA71 RSVD37 AA69 RSVD38 R66 RSVD39 R646 61% 1/16W MF-LF 2 4026 691 18 91 18 91 18 91 18OUT OUT OUT OUT OUT OUT OUT OUTIN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN91 18 91 18 91 18 91 18Embedded DisplayPort (eDP) pins (Auburndale only): eDP_AUX#91 25 8 91 25 91 25 91 25 91 25 91 25 91 25 91 2591 18 91 18 91 18 91 18 91 18 91 18 91 18 91 18OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT8 74 91 91 25 8 74 91 91 25 8 74 91 8 74 91 8 74 91 8 74 91 8 74 91 8 74 91 8 74 91 8 74 91C91 18 91 18 91 18 91 18 91 18 91 18 91 18 91 18PCI EXPRESS -- GRAPHICSFDI_DATA_P&0& FDI_DATA_P&1& FDI_DATA_P&2& FDI_DATA_P&3& FDI_DATA_P&4& FDI_DATA_P&5& FDI_DATA_P&6& FDI_DATA_P&7& FDI_FSYNC&0& FDI_FSYNC&1& FDI_INT FDI_LSYNC&0& FDI_LSYNC&1&K1 N5 N2 R2 N9 R8 U6 W10 AC7 AC9 AB5 AA1 AB2FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1NOTE: HPD must be inverted and level-shifted for Auburndale (1.05V). eDP_HPD# eDP_AUXTP_CPU_RSVD_TP06 6AU1 T4 T2 U1 V2 AV71 AW70 AY69 BB69 D8 B7 A10 B9 C5 A6 E3 F1RESERVEDFDI_DATA_N&0& FDI_DATA_N&1& FDI_DATA_N&2& FDI_DATA_N&3& FDI_DATA_N&4& FDI_DATA_N&5& FDI_DATA_N&6& FDI_DATA_N&7&L2 N7 M4 P1 N10 R7 U7 W8FDI_TX0* FDI_TX1* FDI_TX2* FDI_TX3* FDI_TX4* FDI_TX5* FDI_TX6* FDI_TX7*8 74 91 91 25 8 74 91 91 25 8 74 91 91 25 8 74 91 91 25 8 74 91 91 25CPU_CFG&0& CPU_CFG&1& CPU_CFG&2& CPU_CFG&3& CPU_CFG&4& CPU_CFG&5& CPU_CFG&6& CPU_CFG&7& CPU_CFG&8& CPU_CFG&9& CPU_CFG&10& CPU_CFG&11& CPU_CFG&12& CPU_CFG&13& CPU_CFG&14& CPU_CFG&15& CPU_CFG&16& CPU_CFG&17&AL4 AM2 AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2 AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7CFG0 CFG1 CFG2 C