PEX8624 (PLX) PDF技术资料下载
PEX8624 供应信息 IC Datasheet 数据表 (1/4 页)
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第二代PCIe ， 5.0GT / s的24车道， 6个端口的交换机
[PCIe Gen2, 5.0GT/s 24-lane, 6-port Switch]
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第二代PCIe ， 5.0GT / s的24车道， 6个端口的交换机[PCIe Gen2, 5.0GT/s 24-lane, 6-port Switch]
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Version 0.8 2007FeaturesPEX 8624 General Featureso24-lane, 6-port PCIe Gen2 switch-Integrated 5.0 GT/s SerDeso19 x 19mm2, 324-pin FCBGA packageoTypical Power: & 4.0 WattsPEX 8624PCIe Gen2, 5.0GT/s 24-lane, 6-port SwitchTheExpressLaneTMPEX 8624 device offers PCI Express switchingcapability enabling users to add scalable high bandwidth, non-blockinginterconnection to a wide variety of applications includingworkstations, storage systems, and communications platforms.ThePEX 8624 is well suited forfan-out, aggregation, and peer-to-peerapplications.High Performance & Low Packet LatencyThe PEX 8624 architecture supports packetcut-thru with a maximumlatency of 145ns (x8 to x8).This, combined with large packet memory andnon-blocking internal switch architecture, provides full line rate on all portsfor performance-hungry applications such asserversandswitch fabrics.The low latency enables applications to achieve high throughput andperformance. In addition to low latency, the device supports amax payloadsize of 2048 bytes,enabling the user to achieve even higher throughput.Data IntegrityThe PEX 8624 providesend-to-end CRC(ECRC) protection andPoison bitsupport to enable designs that requireend-to-end data integrity.PLX alsosupports data path parity and memory (RAM) error correction as packetspass through the switch.Flexible Register & Port ConfigurationThe PEX 8624’s 6 ports can be configured to lane widths of x1, x2, x4, orx8. Flexible buffer allocation, along with the device'sflexible packet flowcontrol,maximizes throughput for applications where more traffic flows inthe downstream, rather than upstream, direction. Any port can be designatedas the upstream port, whichx4x8can be changed dynamically.The PEX 8624 also providesseveral ways to configure itsregisters. The device can bePEX 8624PEX 8624configured through strappingpins,I2C interface,hostsoftware, or an optionalx4 x4 x4 x45 x4serial EEPROM. This allowsx8x8for easy debug during thedevelopment phase,performance monitoringPEX 8624during the operation phase,PEX 8624and driver or softwareupgrade. Figure 1 showssome of the PEX 8624’sx8 x4 x4x8x8common port configurations.Figure 1. Common Port ConfigurationsPEX 8624 Key FeaturesoStandards Compliant-PCI Express Base Specification, r2.0(backwards compatible w/ PCIe r1.0a/1.1)-PCI Power Management Spec, r1.2-Microsoft Vista Compliant-Supports Access Control Services-Dynamic link-width control-Dynamic SerDes speed controloHigh Performance-Non-blocking switch fabric-Full line rate on all ports-Packet Cut-Thru with 145ns max packetlatency (x8 to x8)-2KB Max Payload Size-Read Pacing (bandwidth throttling)-Dual-CastoFlexible Configuration-Ports configurable as x1, x2, x4, x8-Registers configurable with strappingpins, EEPROM, I2C, or host software-Lane and polarity reversal-Compatible with PCIe 1.0a PMoDual-Host & Fail-Over Support-Configurable Non-Transparent port-Moveable upstream port-Crosslink port capabilityoQuality of Service (QoS)-Eight traffic classes per port-Weighted round-robin sourceport arbitrationoReliability, Availability, Serviceability-3 Hot Plug Ports with native HP Signals-All ports hot plug capable thru I2C(Hot Plug Controller on every port)-ECRC and Poison bit support-Data Path parity-Memory (RAM) Error Correction-INTA# and FATAL_ERR# signals-Advanced Error Reporting-Port Status bits and GPIO available-Per port error diagnostics-Performance MonitoringoPer port payload & header counters-JTAG AC/DC boundary scanPreliminary - PLX ConfidentialPEX8624 数据表(PDF) - PLX Technology
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