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微星G31主板开机电源及CPU风扇转，无任何显示，无报警声
&&& 该主板型号为：MS-7529 Ver:1.1
&&& 分析检修：从故障现象看，应该是CPU没有工作。装上主板的PCI诊断卡，发现开机后X各输出电压指示正常，但诊断卡显示&FF&即没有跑码，且RST复位指示灯长亮。该主板为INTEL G31芯片组，从INTEL主板的开机时序看，PCI没有复位，如果南桥正常的话，应该是南桥没有收到CPU或是X电源送来的PG信号。尝试开机后，长按&PWWS&键4s后可手动关机，说明南桥及其工作条件基本正常，直接测量主板各路供电，结果发现无CPU核心供电VCCP，部分自绘图如图1所示。该板的VCCP由U3（L6703TR）及其外围电路组成三相供电，查U3的工作条件，上电后测量其15、56、57、62脚的5VSB供电正常，VCCP上推动管Q4,Q17,Q19的12V供电正常，但Q4,Q10,Q17,Q15,Q19,Q20的G极均无任何激励信号，U3供电正常而无驱动信号输出，可见VCCP的VID组合或PWM开启信号异常。先测量U3的17脚（OUTEN）开启信号为0V,测上拉电阻R69上端的VCC-DDR即内存供电为1.91V（正常为1.8V）基本正常，如图1所示，U3的EN开启信号正常应为高电平。测Q13的b极VID_ GD#为0.72V明显异常，正常VID_ GD＃应为低电平。U3的EN信号跟VID组合信号均不正常，显然U3不会有PWM输出。
继续往前级查，正常VID_GD＃为低电平时，Q14应处于饱和导通状态才行，1Q14 b极为0V，明显异常，止常应为高电平，这一高电平是经总线电压V_ FSB_ VTT经R86限流后得到，测R86左端的V_ FSB_TT为0V，正常应为1.2V。总线电压V_& FSB _ VTT由Q24 , U9（LM358）及其外围电路组成。测量Q24的D极VCC DDR为1.91V正常，但Q24的G极为0V，而U9的⑧脚VCC,12V供电为11.89V也正常，在路测量V_& FSB_& VTT对地也无明显的短路，故Q24的G极无激励信号应为U9的③脚无正常的驱动信号或U9本身损坏所致。测U9的③脚电压为0V明显异常。U9为双通道运算放大器，其U9A单元的①、②、③脚及其内部电路与Q24及其外部电路组成闭环电压调节器，U9A的反相输入端②脚接到调节器输出端Q24的S极，把V_& FSB _ VTT作为反馈稳压信号；正相输入端③脚接偏置电阻R160,R162,R154，改变R160,R162的阻值大小，即改变U9A的③脚电位，经内部比较处理后控制Q24的导通程度，从而使Q24的S极输出电压可控制、稳定。测R154的左端也为0V，再测量R160上端V_1P5_MCH还是0V,所以故障还在前级。
&&& 如图2所示，V 1P5es MCH由U11及其外围电路组成，从电路图分析，V 1P5ee MCH除了直接为北桥提供CCD_ CRT,VCCDQ CRT外，还为北桥的核心供电V 1P25_ CORE及南桥的核心供电V 1P5_ CORE提供触发开启信号。此信号异常肯定会引起上述供电异常，试测V 1P5_ CORE只有0.443V明显异常。在路测V 1P5_ MCH对地无明显短路，测U11的①脚供电VIN为3.39V，基本正常，其②脚EN开启信号为2.5V也正常。但其⑤、④脚均为0V。查反馈电阻R187(18k&O), R184 (20k&O)均正常，显然是U11本身性能不良而导致其⑤脚无输出电压。
&&& 查图纸得知U11为UP7707（SOT-23封装）5脚贴片电压调节器，如图3所示，实物芯片上并未标注UP7707而是用贴片代码：S2 00/PLA87A表示。因无原型号元件，故考虑代换。
&&& 经查找，发现华硕笔记本A8T/M的料板上有类似5脚贴片元件，仔细查A8T/M的点位图，如图4所示，发现PU6401（印字A93AJ）的①脚接3V电压，②脚接地，③脚直接与①脚连接，④脚一路与电阻PR6414连接，PR6414另一端接地；另一路与PR6411连接，PR6411另一端与PU6401的⑤脚连接，而⑤脚外接有滤波电容PC6408，且PCB上有巧P644这样的堆锡断路点（笔记本各供电支路中，一般都设置有这种维修点，可方便断开其负载电路进行检测），所以判断应该为输出电压端。对比发现，除了③脚，其他4个脚外接电路与MS-7529的U11电路完全相同。从实际的电路分析：如果该芯片的③脚也为EN开启端口，则该电路中直接把EN接到3V，相当于只要PU6401的①脚有3V供电，其③脚就有开启电压，从而使其⑤脚有输出电压，该电压大小由PU6401的外接反馈电阻PR6414, PR6411大小决定。
&&& 查A8T/M电路确定PU6401的输出电压为1.5V;考虑到两种芯片的参数差异，为了保险起见，同时拆除A8T/M电路板上的PU6401, PR6411, PR6414，对应代换本板的U11,R187,R184。因PR6411, PR6414的体积比R187,R184稍大，故只能把PR6411、PR6414侧立焊接，检查无误后开机，V 1P5es MCH为1.5V稳定。装上CPU、内机后，开机顺利跑码，显示&OK&。焊接好的实物如图5所示。
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微星主板ms-96A8-0A图纸
Cover Sheet Block Diagram Intel Diamondville CPU
1 2 3-4 5-8 9 10-11 12 13 14 15 16 17 21 22 23 24 23 25 26-29 30-31 32-33
CPU: Intel Diamondville Processor System Chipset: Intel 945 GSE (North Bridge) Intel ICH7-M (South Bridge) On Board Chipset: Clock Generator - ICS954129 Differential Buffer -- DB800 LPC Super I/O -- W83627EHG LAN -- INTEL 82573L * 4 BIOS -- FWH EEPROM
Version 0A 01/14/2008 REV-0A
Intel 945GSE Intel ICH7-M - CPU&LPC&SATA&Azalia
Intel ICH7-M - GPIO&PCIE&USB&POWER
Clock -ICS954129 & FWH & SPI LPC I/O - W83627EHG DDR2 System Memory DDR Termination Resistors
PCI Slot USB Connectors ATX , VGA Connetcors & Front Panel MS-7 ACPI Controller & MS-11 SATA & CF & DOM CONNECTORS FAN CONNECTORS CPU Power
LAN1 & 2 & 3 & 4 -- INTEL 82573L LAN1 & 2 & 3 & 4 -- RELAY
Main Memory: DDR 2 (Max 2GB) Expansion Slots: PCI EXPRESS X4 SLOT PCI2.3 SLOT * 1 V-core PWM: IMVP-6 Controller: ISL6262 System power PWM: MS-7 & MS-11
Golden Finger GPIO & JUMPER SETTTING MANUAL PARTS Power MAP
34 35 36 37 38 39 40 41
CLOCK MAP POWER SEQUENCE SMBUS MAP CHANGE HISTORY
MICRO-STAR INT'L CO.,LTD
Size Custom
Document Description
Cover Sheet
Rev 0A 1 of 40
Date: Monday, March 10, 2008
Intel Diamondville Processor
Block Diagram
533/667MHz
PCI EXPRESS X 4 (Golden Finger) TV-out CRT CF connector - Master DOM connector - Slave SATA 1~2 CRT
945GSE Calistoga
400/533/667MHz
S0-DIMM Modules
UltraDMA 33/66/100
PCI Slot x 1
USB Port 0~3
LAN Intel 82573L
LAN Intel 82573L * Flash
Lan interface
GOLDEN FINGER LAN interface
LPC SIO Winbond 83627EHG
MICRO-STAR INT'L CO.,LTD
..... ....
Size Custom
Document Description
Block Diagram
Rev 0A 2 of 40
Date: Monday, March 10, 2008
HA#[3..31]
HA#[3..31]
HREQ#[0..4]
HREQ#[0..4]
U23A HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HASTB#0 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HA#32 HA#33 HA#34 HA#35 HASTB#1 T21 P21 H20 N20 R20 J19 N19 G20 M19 H21 L20 M20 K19 J20 L21 K20 D17 N21 J21 G19 P20 R19 C19 F19 E21 A16 D19 C14 C18 C20 E20 D20 B18 C15 B16 B17 C16 A17 B14 B15 A14 B19 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# AP0 REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# IERR# INIT# LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# HIT# HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# BR1# PROCHOT# THERMDA THERMDC V19 Y19 U21 T21 T19 Y18 T20 F16 V16 W20 D15 W18 Y17 U20 W19 AA17 V20 K17 J18 H15 J15 K18 J16 M17 N16 M16 L17 K16 V15 H_ADS# H_BNR# H_BPRI# H_DEFER# H_DRDY# H_DBSY# H_BR#0 H_IERR# H_INITR# H_LOCK# RS#0 RS#1 RS#2 H_TRDY# H_HIT# H_HITM# BI BI IN IN BI BI BI R362 BI IN RS#0 RS#1 RS#2 IN BI BI H_ADS# H_BNR# H_BPRI# 8 8 8 U23B 8 HD#[63:0] BI HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 BI BI BI BI Y11 W10 Y12 AA14 AA11 W12 AA16 Y10 Y9 Y13 W15 AA13 Y16 W13 AA9 W9 Y14 Y15 W16 DP#0 V9 AA5 Y8 W3 U1 W7 W6 Y7 AA6 Y3 W2 V3 U2 T3 AA8 V2 W4 Y4 Y5 Y6 DP#1 R4 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DP#0 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# DP#1 GTLREF ACLKPH DCLKPH BINIT# EDM EXTBGR FORCEPR# HFPLL MCERR# RSP# D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DP#2 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# DP#3 COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# CORE_D CMREF BSEL[0] BSEL[1] BSEL[2] R3 R2 P1 N1 M2 P2 J3 N3 G3 H2 N2 L2 M3 J2 H1 J1 K2 K3 L1 M4 C2 G2 F1 D3 B4 E1 A5 C3 A6 F2 C6 B6 B3 C4 C7 D2 E2 F3 C5 D4 T1 T2 F20 F21 R18 R17 U4 V17 N18 A13 B7 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 BI HD#[63:0] 8
H_BR#0 1K_1% H_LOCK#
8 IN 8 H_INIT# 9
H_CPURST# 8 8 8 8 H_TRDY# 8 H_HIT# H_HITM# 8 8 8
XDP/ITP SIGNALS
ADDR GROUP 0
H_DEFER# 8 H_DRDY# 8 H_DBSY# 8
HDSTBN#0 HDSTBP#0 DBI#0 HD#[63:0]
T16 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 BI BI BI
T8 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
BI BI BI BI
HDSTBN#2 8 HDSTBP#2 8 DBI#2 8 HD#[63:0] 8
ADDR GROUP 1
V_FSB_VTT RN54
2 4 6 8 1K-8P4R
HA#32 HA#34 HA#33 HA#35
PREQ# H_TCK H_TDI H_TDO H_TMS H_TRST# 22
TP11 TP2 R216 R221 68 IN H_PROCHOT# 22 8 8 8 TRMTRIP# 6,9 HDSTBN#1 HDSTBP#1 DBI#1
PROCHOT# G17 THERMDA E4 THERMDC E5
DP#3 HCOMP0 HCOMP1 HCOMP2 HCOMP3
HDSTBN#3 8 HDSTBP#3 8 DBI#3 8 R324 R360 R375 R374 27.4_1% 54.9_1% 27.4_1% 54.9_1%
0.5& max length
25 MIL AWAY FROM HIGH SPEED SIGNAL HCOMP0,2==&18MIL HCOMP1,3==&5MIL
AP1 M18 U18 T16 J4 H_STPCLK# R16 T15 R15 U17
AP1 A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI#
THERMTRIP#
H17 TRMTRIP#
R351 R685 V_FSB_VTT T18 T15 T12 T17 T14 T20 T13
9 9 9 9 9 9 9
H_A20M# H_FERR# H_IGNNE# H_STPCLK# H_INTR H_NMI ICH_H_SMI#
IN OUT IN IN IN IN IN
BCLK[0] BCLK[1]
CK_H_CPU CK_H_CPU#
CK_H_CPU 12 CK_H_CPU# 12
H_IERR# PREQ# H_TMS H_TCK H_TDI
CPU_GTLREF A7 X_1K U5 X_1K V5 BINIT# T17 EDM R6 EXTBGREF M6 FORCEPR# N15 HFPLL N6 MCERR# P17 RSP# T6
V_FSB_VTT R365 R350 R356 R361 1K 1K X_51 X_51 H_A20M# H_IGNNE# H_INTR H_NMI
D6 G6 H6 K4 K5 M15 L16
NC1 NC2 NC3 NC4 NC5 NC6 NC7
2 4 6 8 56-8P4R
H_DPRSTP# H_DPSLP# H_DPWR# CPU_PWRGD CPUSLP# CORE_D T33 CPU_CMREF
IN IN IN IN IN
H_DPRSTP# 9,22 H_DPSLP# 9 H_DPWR# 8 CPU_PWRGD 9 CPUSLP# 8
RSVD3 RSVD2 RSVD1
C21 C1 A3 H_TRST# R382
6,12 6,12 6,12
BSEL0 BSEL1 BSEL2
56 Diamondville
Diamondville V_FSB_VTT V_FSB_VTT
0.5& max length
VCC3 SM_LINK0 SM_LINK1 R129 R134 2.2K 2.2K R327 2K_1% C629 1u_6.3V R364 2K_1% R328 1K_1% EXTBGREF R366 1K_1%
0.5& max length
0.5& max length
R353 1K_1% CPU_GTLREF CPU_CMREF C630 0.1u_10V R352 2K_1%
Cap close to thermal sensor
Close to CPU socket
VCC3 U40 THERMDA C121 2200p_50V THERMDC TRMTRIP# R146 X_0 C116 0.1u_10V 1 2 3 4 VDD SMBCLK D+ SMBData DALERT T_CRIT_A GND 8 7 6 5
C631 X_0.1u_10V
SM_LINK0 SM_LINK1 LINK_ALERT#
SM_LINK0 10,32 SM_LINK1 10,32 LINK_ALERT# 10
SNSR-LM95245CIMM-RH
MICRO-STAR INT'L CO.,LTD
Document Description
CPU_Diamondville_signal
Rev 0A 3 of 40
Date: Monday, March 10, 2008
U23D A2 A4 A8 A15 A18 A19 A20 B1 B2 B5 B8 B13 B20 B21 C8 C17 D1 D5 D8 D14 D18 D21 E3 E6 E7 E8 E15 E16 E19 F4 F5 F6 F7 F17 F18 G1 G4 G7 G9 G13 G21 H3 H4 H7 H9 H13 H16 H18 H19 J5 J7 J9 J13 J17 K1 K6 K7 K9 K13 K15 K21 L3 L4 L5 L6 L7 L9 L13 L15 L18 L19 M1 M5 M7 M9 M13 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS V_FSB_VTT VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N9 N7 N5 N4 M21 N13 N17 P3 P4 P5 P6 P7 P9 P13 P15 P16 P18 P19 R1 R5 R7 R9 R13 R21 T4 T5 T7 T9 T10 T11 T12 T13 T18 U3 U6 U7 U15 U16 U19 V1 V4 V6 V7 V8 V13 V14 V18 V21 W1 W5 W8 W11 W14 W17 W21 Y1 Y2 Y20 Y21 AA2 AA3 AA4 AA7 AA10 AA12 AA15 AA18 AA19 AA20 U23C V10 A9 B9 VCORE VCCF VCCQ1 VCCQ2 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VCCPC64 VCCPC63 VCCPC62 VCCPC61 VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE C9 D9 E9 F8 F9 G8 G14 H8 H14 J8 J14 K8 K14 L8 L14 M8 M14 N8 N14 P8 P14 R8 R14 T8 T14 U8 U9 U10 U11 U12 U13 U14 F14 F13 E14 E13 V_FSB_VTT
C222 0.1u_10V
C198 1u_6.3V
C220 1u_6.3V
C227 10u_6.3V
C237 10u_6.3V_0805
A10 A11 A12 B10 B11 B12 C10 C11 C12 D10 D11 D12 E10 E11 E12 F10 F11 F12 G10 G11 G12 H10 H11 H12 J10 J11 J12 K10 K11 K12 L10 L11 L12 M10 M11 M12 N10 N11 N12 P10 P11 P12 R10 R11 R12
VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9 VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21 VCCP22 VCCP23 VCCP24 VCCP25 VCCP26 VCCP27 VCCP28 VCCP29 VCCP30 VCCP31 VCCP32 VCCP33 VCCP34 VCCP35 VCCP36 VCCP37 VCCP38 VCCP39 VCCP40 VCCP41 VCCP42 VCCP43 VCCP44 VCCP45
Place in cavity
Place in cavity
C223 1u_6.3V
C224 1u_6.3V
C238 1u_6.3V
C239 1u_6.3V
C240 1u_6.3V
C245 1u_6.3V
C253 1u_6.3V
V_1P5_CORE VCORE C246 0.1u_16V
D7 F15 D16 E18 G15 G16 E17 G18 C13 D13 R691 100_1% CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 OUT OUT OUT OUT OUT OUT OUT CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 22 22 22 22 22 22 22 VCORE
C260 1u_6.3V
C261 1u_6.3V
C264 1u_6.3V
C197 1u_6.3V
C217 1u_6.3V
C221 1u_6.3V
R690 100_1%
VCCSENSE VSSSENSE
2.5A: before VCC stable 1.5A: after VCC stable
Diamondville
Place in cavity
C244 10u_6.3V_0805
C249 10u_6.3V_0805
C254 10u_6.3V_0805
Diamondville
LAYOUT NOTE: Route VCCSENSE and VSSSENSE traces at 27.4Ohms with 50 mil spacing. Place PU and PD within 1 inch of CPU.
close to cpu socket
MICRO-STAR INT'L CO.,LTD
Document Description
CPU _Diamondville_Power/GND
Rev 0A of 40
Date: Monday, March 10, 2008
U26D V_FSB_VTT 1 + 2 EC29 C220u6.3-RH V_1P5_CORE C229 10u_6.3V_.7u_6.3V_.7u_6.3V_.1u_10V C204 0.1u_10V C219 0.1u_10V T26 R26 P26 N26 M26 V19 U19 T19 W18 V18 T18 R18 W17 U17 R17 W16 V16 T16 R16 V15 U15 T15 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AC27 AD26 AC26 AB26 AE19 AE18 AF17 AE17 AF16 AE16 AF15 AE15 J14 J10 H10 AE9 AD9 U9 AD8 AD7 AD6 0.47u_10V A14 D10 P9 L9 D9 P8 L8 D8 P7 L7 D7 A7 P6 L6 G6 D6 U5 P5 L5 G5 D5 Y4 U4 P4 L4 G4 D4 Y3 U3 P3 L3 G3 D3 Y2 U2 P2 L2 G2 D2 AA1 F1 VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25 VTT26 VTT27 VTT28 VTT29 VTT30 VTT31 VTT32 VTT33 VTT34 VTT36 VTT35 VTT37 VTT38 VTT39 VTT40 VCCATVDACA0 VCCATVDACA1 VCCATVDACB0 VCCATVDACB1 VCCATVDACC0 VCCATVDACC1 VCCATVBG VSSATVBG VCCDTVDAC VCCDQTVDAC VCCDLVDS0 VCCDLVDS1 VCCDLVDS2 VCCHV0 VCCHV1 VCCHV2 VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCAMPLL VCCAHPLL VCCADPLLA VCCADPLLB VCCDHMPLL1 VCCDHMPLL2 VCCTXLVDS0 VCCTXLVDS1 VCC3G0 VCC3G1 VCCA3GPLL VCCA3GBG VSSA3GBG VCCSYNC VCCACRTDAC0 VCCACRTDAC1 VSSACRTDAC VCCALVDS VSSALVDS VTT41 VTT42 VTT43 VTT44 VTT45 B20 A20 B22 A22 D22 C22 D23 E23 F20 F22 C28 B28 A28 E26 D26 C26 AB33 AM32 AN29 AM29 AL29 AK29 AJ29 AH29 AG29 AF29 AE29 AN24 AM24 AL24 AK24 AJ24 AH24 AG24 AF24 AE24 AN18 AN16 AM16 AL16 AK16 AJ16 AN13 AM13 AL13 AK13 AJ13 AH13 AG13 AF13 AE13 AN4 AM10 AL10 AK10 AH1 AH10 AG10 AF10 AE10 AN7 AM7 AL7 AK7 AJ7 AH7 AN10 AJ10 AD1 AD2 B26 J32 AE5 AD5 D29 C29 U33 T33 V26 N33 M33 J23 C24 B24 B25 B31 B32 P1 L1 G1 U1 Y1 C373 C265 0.022u_16V 0.1u_10V
V_1P5_CORE C252 0.1u_10V C251 20mA 10u_6.3V_0805
L12 +1_5VRUN_DPLLA 120L600mA-250 1
+ EC30 100u_6.3V_SOLID C345 0.1u_10V +1_5VRUN_DPLLB
VCC3 C250 0.1u_10V C288 1u_6.3V C190 1u_6.3V C241 10u_6.3V_0805
CP21 X_COPPER L14 120L600mA-250
1 + EC31 100u_6.3V_SOLID C332 0.1u_10V +1_5VRUN_HPLL V_1P5_CORE
CP22 X_COPPER L15 120L600mA-250
C337 2.2u_6.3V C347 0.1u_10V +1_5VRUN_MPLL
1250mA DDR2 DLL DDR2 FSB HSIO
C287 0.1u_10V
CP25 X_COPPER L16 120L600mA-250
VCC_DDR2 C353 1u_6.3V C349 1u_6.3V EC32 C354 C348 4.7u_6.3V_.3V_V_SOLID 2 +1
C343 2.2u_6.3V C335 0.1u_10V
Place in cavity
CP26 X_COPPER
Place close to 945GMS
C327 V_FSB_VTT C325 C326 4.7u_6.3V_.3V_0805
C322 1u_6.3V C320 1u_6.3V
Place in cavity
V_1P5_CORE L9 91n1.5A_u_6.3V_0805
V_2P5_MCH C192 0.1u_10V +1_5VRUN_MPLL +1_5VRUN_HPLL +1_5VRUN_DPLLA +1_5VRUN_DPLLB V_1P5_CORE C330 0.1u_10V VCCA_3GPLL
+1_5VRUN_PCIE C328 0.47u_10V C262 10u_6.3V_.2u_6.3V
C191 4.7u_6.3V_0805
L10 1u500mA_0805 VCCA_3GPLL
+1_5VRUN_PCIE
C329 10u_6.3V_0805
V_2P5_MCH V_2P5_MCH D14 C302 0.1u_10V C303 10u_6.3V_0805 V_FSB_VTT S-RB551V-30 10 CP14 X_COPPER C147 10u_6.3V_ V_2P5_MCH L17 100L3A
V_2P5_MCH V_FSB_VTT D13 R337 10 L11 180L_1.5A-90 C268 10u_6.3V_0805
VCCA_CRTDAC
VCCA_CRTDAC
S-RB551V-30
V_FSB_VTT C313 0.022u_16V
VCCA_CRTDAC C316 0.1u_10V
C357 0.47u_10V
C356 0.47u_10V
C323 0.01u_16V
V_2P5_MCH C324 0.1u_10V
MICRO-STAR INT'L CO.,LTD
Document Description
MCH_945GMS (POWER)
Rev 0A 5 of 40
Date: Monday, March 10, 2008
VGA_BLUE VGA_GREEN VGA_RED R326 150_1% VCC3 R333 150_1% R335 150_1%
R194 2.2K U26B 10 10 10 10 10 10 10 10 DMIRXN0 DMIRXN1 DMIRXP0 DMIRXP1 DMITXN0 DMITXN1 DMITXP0 DMITXP1 IN IN IN IN OUT OUT OUT OUT Y29 Y32 Y28 Y31 V28 V31 V29 V32 DMI_RXN_0 DMI_RXN_1 DMI_RXP_0 DMI_RXP_1 DMI_TXN_0 DMI_TXN_1 DMI_TXP_0 DMI_TXP_1 CFG_0 CFG_1 CFG_2 CFG_3 CFG_5 CFG_6 C18 MCH_BSEL0 E18 MCH_BSEL1 G20 MCH_BSEL2 CFG3 G18 CFG5 J20 CFG6 J18 R289 X_2.2K BI BSEL0 3,12 BI BI R282 2.2K R275 2.2K R301 X_2.2K BSEL1 BSEL2 3,12 12 CK_PE_100M_MCH# 3,12 12 CK_PE_100M_MCH IN IN H27 J27 Y26 AA26
U26F SDVO_CTRLDATA SDVO_CTRLCLK G_CLKN G_CLKP EXP_A_COMPI EXP_A_ICOMPO SDVO_TVCLKIN# SDVO_INT# SDVO_FLDSTALL# SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL R28 M28
18 MCH_DDC_CLK 18 MCH_DDC_DATA 18 VGA_BLUE 18 18 VGA_GREEN VGA_RED R308 R303 39 39
BI BI OUT OUT OUT
MCH_DDC_CLK MCH_DDC_DATA VGA_BLUE VGA_GREEN VGA_RED VSYNC_R HSYNC_R R307 255_1%_0603
15 15 14 14 15 15
SM_CK_B1 SM_CK_B2 SM_CK#_A1 SM_CK#_A2 SM_CK#_B1 SM_CK#_B2
OUT OUT OUT OUT OUT OUT 14,16 SCKE_A0 14,16 SCKE_A1 15,16 SCKE_B0 15,16 SCKE_B1 14,16 14,16 15,16 15,16 SCS_A#0 SCS_A#1 SCS_B#0 SCS_B#1 OUT OUT OUT OUT OUT OUT OUT OUT
AJ1 AM30 AG33 AF1 AK1 AN30 AN21 AN22 AF26 AF25 AG14 AF12 AK14 AH12 AJ21 AF11 14,16 14,16 15,16 15,16 ODT_A0 ODT_A1 ODT_B0 ODT_B1 OUT OUT OUT OUT M_RCOMPN M_RCOMPP 945GMDDR_VREF AE12 AF14 AJ14 AJ12 AN12 AN14 AA33 AE1
SM_CK_2 SM_CK_3
VSYNC HSYNC
SM_CK_A1 SM_CK_A2
SM_CK_0 SM_CK_1
RESERVED1 RESERVED2 RESERVED7 RESERVED8 RESERVED9
K32 K31 C17 F18 A3
H20 H22 A24 A23 E25 F25 C25 D25 F27 D27 H25 H30 G29 F28 E28 G28 H28 K30 K27 J29 J30 K29 D30 C30 A30 A29 G31 F32 D31 H31 G32 C31 F33 D33 F30 E33 D32 F29
N30 R30 T29 M30 P30 T30
CRT_DDC_CLK CRT_DDC_DATA CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# CRT_VSYNC CRT_HSYNC CRT_IREF L_BKLTCTL L_BKLTEN L_CLKCTLA L_CTLBDATA L_DDC_CLK L_DDC_DATA L_VDDEN L_IBG L_VBG L_VREFH L_VREFL LA_CLKN LA_CLKP LB_CLKN LB_CLKP LA_DATAN_0 LA_DATAN_1 LA_DATAN_2 LA_DATAP_0 LA_DATAP_1 LA_DATAP_2 LB_DATAN_0 LB_DATAN_1 LB_DATAN_2 LB_DATAP_0 LB_DATAP_1 LB_DATAP_2
SM_CK#_2 SM_CK#_3 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3
DDR2 MUXING
SM_CK#_0 SM_CK#_1
SDVO_RED# SDVO_GREEN# SDVO_BLUE# SDVO_CLKN SDVO_RED SDVO_GREEN SDVO_BLUE SDVO_CLKP
P28 N32 P32 T32 N28 M32 P33 R32 V_1P5_CORE
VCC3 PM_ICHSYNC# PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 THRMTRIP# PWROK RSTIN# E31 G21 F26 H26 J15 AB29 W27 MCH_ICH_SYNC# BI MCH_ICH_SYNC# BM_BUSY# OUT BM_BUSY# 10 PM_EXTTS#0 R147 DPRSLPVR IN DPRSLPVR 10,22 OUT TRMTRIP# 3,9 IN PWRGD 10,19,22 IN DEV_RST# 13,19,31 9 10K/4
SM_OCDCOMP_0 SM_OCDCOMP_1 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_RCOMPN SM_RCOMPP SM_VREF_0 SM_VREF_1
TV_DACA TV_DACB TV_DACC TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC
A21 C20 E20 G23 B21 C21 D21
Disable TV
80.6_1%__1%_0603
D_REFCLKN D_REFCLKP D_REFSSCLKN D_REFSSCLKP CLKREQ# A27 IN A26 IN J33 H33 J22 MCH_CLKREQ# CK_96M_DREF# 12 CK_96M_DREF 12 R115 R188 0 0 V_1P5_CORE VCC3
TV_DCONSEL0 TV_DCONSEL1
R203 10K_1%
945GMDDR_VREF
CLKREQ#: Driven by GMCH to control the PCIe clock to External Graphics and the DMI clock.
R204 10K_1% MCH_CLKREQ# C189 0.1u_10V
R315 X_10K
as close as 945GM
DPRSLPVR: Enable power savings by speeding up the C4 exit latency.
VCC3 DPRSLPVR R299 10K
un-stuffed, if support C4E feature.
MICRO-STAR INT'L CO.,LTD
Document Description
MCH_945GMS (DMI/VGA)
Rev 0A 6 of 40
Date: Monday, March 10, 2008
V_1P5_CORE 14,15 DATA_A[63:0] U26C DATA_A0 DATA_A1 DATA_A2 DATA_A3 DATA_A4 DATA_A5 DATA_A6 DATA_A7 DATA_A8 DATA_A9 DATA_A10 DATA_A11 DATA_A12 DATA_A13 DATA_A14 DATA_A15 DATA_A16 DATA_A17 DATA_A18 DATA_A19 DATA_A20 DATA_A21 DATA_A22 DATA_A23 DATA_A24 DATA_A25 DATA_A26 DATA_A27 DATA_A28 DATA_A29 DATA_A30 DATA_A31 DATA_A32 DATA_A33 DATA_A34 DATA_A35 DATA_A36 DATA_A37 DATA_A38 DATA_A39 DATA_A40 DATA_A41 DATA_A42 DATA_A43 DATA_A44 DATA_A45 DATA_A46 DATA_A47 DATA_A48 DATA_A49 DATA_A50 DATA_A51 DATA_A52 DATA_A53 DATA_A54 DATA_A55 DATA_A56 DATA_A57 DATA_A58 DATA_A59 DATA_A60 DATA_A61 DATA_A62 DATA_A63 CAS_B# RAS_B# WE_B# AC31 AB28 AE33 AF32 AC33 AB32 AB31 AE31 AH31 AK31 AL28 AK27 AH30 AL32 AJ28 AJ27 AH32 AF31 AH27 AF28 AJ32 AG31 AG28 AG27 AN27 AM26 AJ26 AJ25 AL27 AN26 AH25 AG26 AM12 AL11 AH9 AK9 AM11 AK11 AM8 AK8 AG9 AF9 AF8 AK6 AF7 AG11 AJ6 AH6 AN6 AM6 AK3 AL2 AM5 AL5 AJ3 AJ2 AG2 AF3 AE7 AF6 AH5 AG3 AG5 AF5 AG19 AG21 AG20 SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SB_CAS# SB_RAS# SB_WE# SA_BS_0 SA_BS_1 SA_BS_2 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# SB_BS_0 SB_BS_1 SB_BS_2 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 AK12 AH11 AG17 AB30 AL31 AF30 AK26 AL9 AG7 AK5 AH3 AC28 AJ30 AK33 AL25 AN9 AH8 AM2 AE3 AC29 AK30 AJ33 AM25 AN8 AJ8 AM3 AE2 AJ15 AM17 AM15 AH15 AK15 AN15 AJ18 AF19 AN17 AL17 AG16 AL18 AG18 AL14 AJ17 AK18 AN28 AM28 AH17 AH21 AJ20 AE27 AN20 AL21 AK21 AK22 AL22 AH22 AG22 AF21 AM21 AE21 AL20 AE22 AE26 AE20 MAA_B0 MAA_B1 MAA_B2 MAA_B3 MAA_B4 MAA_B5 MAA_B6 MAA_B7 MAA_B8 MAA_B9 MAA_B10 MAA_B11 MAA_B12 MAA_B13 MAA_A0 MAA_A1 MAA_A2 MAA_A3 MAA_A4 MAA_A5 MAA_A6 MAA_A7 MAA_A8 MAA_A9 MAA_A10 MAA_A11 MAA_A12 MAA_A13 DQS_A#0 DQS_A#1 DQS_A#2 DQS_A#3 DQS_A#4 DQS_A#5 DQS_A#6 DQS_A#7 SBS_A0 SBS_A1 SBS_A2 14,16 14,16 14,16 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 V_FSB_VTT U26H T25 R25 P25 N25 M25 P24 N24 M24 Y22 W22 V22 U22 T22 R22 P22 N22 M22 Y21 W21 V21 U21 T21 R21 P21 N21 M21 Y20 W20 V20 U20 T20 R20 P20 N20 M20 Y19 P19 N19 M19 Y18 P18 N18 M18 Y17 P17 N17 M17 Y16 P16 N16 M16 Y15 P15 N15 M15 Y14 W14 V14 U14 T14 R14 P14 N14 M14 V_FSB_VTT T10 R10 P10 N10 L10 D1 M10 A18 AB10 AA10 945GMS
DQM_A0 DQM_A1 DQM_A2 DQM_A3 DQM_A4 DQM_A5 DQM_A6 DQM_A7 DQS_A0 DQS_A1 DQS_A2 DQS_A3 DQS_A4 DQS_A5 DQS_A6 DQS_A7
DDR2 SYSTEM MEMORY
14,15 14,15 14,15 14,15 14,15 14,15 14,15 14,15 MAA_A[0..13]
CAS_A# RAS_A# TP13 WE_A# SBS_B0 SBS_B1 SBS_B2
14,16 14,16 14,16
15,16 15,16 15,16 MAA_B[0..13]
VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VTT_NCTF1 VTT_NCTF2 VTT_NCTF3 VTT_NCTF4 VTT_NCTF5 VTT_NCTF6 RSVD_3 RSVD_4 RSVD_5 RSVD_6
VCCAUX_NCTF1 VCCAUX_NCTF2 VCCAUX_NCTF3 VCCAUX_NCTF4 VCCAUX_NCTF5 VCCAUX_NCTF6 VCCAUX_NCTF7 VCCAUX_NCTF8 VCCAUX_NCTF9 VCCAUX_NCTF10 VCCAUX_NCTF11 VCCAUX_NCTF12 VCCAUX_NCTF13 VCCAUX_NCTF14 VCCAUX_NCTF15 VCCAUX_NCTF16 VCCAUX_NCTF17 VCCAUX_NCTF18 VCCAUX_NCTF19 VCCAUX_NCTF20 VCCAUX_NCTF21 VCCAUX_NCTF22 VCCAUX_NCTF23 VCCAUX_NCTF24 VCCAUX_NCTF25 VCCAUX_NCTF26 VCCAUX_NCTF27 VCCAUX_NCTF28 VCCAUX_NCTF29 VCCAUX_NCTF30 VCCAUX_NCTF31 VCCAUX_NCTF32 VCCAUX_NCTF33 VCCAUX_NCTF34 VCCAUX_NCTF35 VCCAUX_NCTF36 VCCAUX_NCTF37 VCCAUX_NCTF38 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 VSS_NCTF8 VSS_NCTF9 VSS_NCTF10 VSS_NCTF11 VSS_NCTF12 VSS_NCTF13 VSS_NCTF14 VSS_NCTF15 VSS_NCTF16 VSS_NCTF17 VSS_NCTF18 VSS_NCTF19 CFG_19 RESERVED10 RESERVED11 RESERVED12 RESERVED13 RESERVED14 RESERVED15 RESERVED16 RESERVED17 RESERVED18 RESERVED19 RESERVED20 RESERVED21 RESERVED22 RESERVED23 RESERVED24 RESERVED25
AD25 AC25 AB25 AD24 AC24 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 K14 AD13 Y13 W13 V13 U13 T13 R13 P13 N13 M13 AD12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 AD11 AD10 K10 AN33 AA25 V25 U25 AA22 AA21 AA20 AA19 AA18 AA17 AA16 AA15 AA14 AA13 A4 A33 B2 AN1 C1 K28 K25 K26 R24 T24 K21 K19 K20 K24 K22 J17 K23 K17 K12 K13 K16 K15
15,16 15,16 15,16
CAS_B# RAS_B# WE_B#
945GMS U26E
R1 V1 F2 H2 K2 M2 AB2 AF2 AH2 AK2 B3 T3 W3 AD3 AL3 E4 H4 K4 N4 R4 V4 AA4 B5 AJ5 AN5 K6 M6 T6 W6 AB6 AE6 AG6 AL6 B7 E7 H7 N7 R7 V7 AA7 U8 AE8 AG8 AL8 A9 C9 F9 J9 M9 R9 W9 AB9 AJ9 AM9 AE11 AJ11 AN11 B12 H12 AG12 AL12 D13 F13 B14 H14 AE14 AH14 AM14 D15 F15 R15 W15 AG15 AL15 J16
VSS_185 VSS_184 VSS_183 VSS_182 VSS_181 VSS_180 VSS_179 VSS_178 VSS_177 VSS_176 VSS_175 VSS_174 VSS_173 VSS_172 VSS_171 VSS_170 VSS_169 VSS_168 VSS_167 VSS_166 VSS_165 VSS_164 VSS_163 VSS_162 VSS_161 VSS_160 VSS_159 VSS_158 VSS_157 VSS_156 VSS_155 VSS_154 VSS_153 VSS_152 VSS_151 VSS_150 VSS_149 VSS_148 VSS_147 VSS_146 VSS_145 VSS_144 VSS_143 VSS_142 VSS_141 VSS_140 VSS_139 VSS_138 VSS_137 VSS_136 VSS_135 VSS_134 VSS_133 VSS_132 VSS_131 VSS_130 VSS_129 VSS_128 VSS_127 VSS_126 VSS_125 VSS_124 VSS_123 VSS_122 VSS_121 VSS_120 VSS_119 VSS_118 VSS_117 VSS_116 VSS_115 VSS_114 VSS_113 VSS_112 VSS_111
VSS_110 VSS_109 VSS_108 VSS_107 VSS_106 VSS_105 VSS_104 VSS_103 VSS_102 VSS_101 VSS_100 VSS_99 VSS_98 VSS_97 VSS_96 VSS_95 VSS_94 VSS_93 VSS_92 VSS_91 VSS_90 VSS_89 VSS_88 VSS_87 VSS_86 VSS_85 VSS_84 VSS_83 VSS_82 VSS_81 VSS_80 VSS_79 VSS_78 VSS_77 VSS_76 VSS_75 VSS_74 VSS_73 VSS_72 VSS_71 VSS_70 VSS_69 VSS_68 VSS_67 VSS_66 VSS_65 VSS_64 VSS_63 VSS_62 VSS_61 VSS_60 VSS_59 VSS_58 VSS_57 VSS_56 VSS_55 VSS_54 VSS_53 VSS_52 VSS_51 VSS_50 VSS_49 VSS_48 VSS_47 VSS_46 VSS_45 VSS_44 VSS_43 VSS_42 VSS_41 VSS_40 VSS_39 VSS_38 VSS_37 VSS_36 VSS_35 VSS_34 VSS_33 VSS_32 VSS_31 VSS_30 VSS_29 VSS_28 VSS_27 VSS_26 VSS_25 VSS_24 VSS_23 VSS_22 VSS_21 VSS_20 VSS_19 VSS_18 VSS_17 VSS_16 VSS_15 VSS_14 VSS_13 VSS_12 VSS_11 VSS_10 VSS_9 VSS_8 VSS_7 VSS_6 VSS_5 VSS_4 VSS_3 VSS_2 VSS_1
U16 AH16 B17 F17 T17 V17 AK17 D18 H18 U18 AF18 AH18 AM18 R19 W19 D20 AF20 AH20 AK20 AM20 F21 H21 J21 E22 G22 AF22 AJ22 AM22 B23 F23 H23 A25 G25 J25 AE25 AG25 AK25 AN25 U26 W26 AH26 AL26 B27 C27 E27 G27 M27 N27 P27 R27 T27 U27 Y27 AA27 AB27 AF27 AM27 D28 J28 T28 U28 AA28 AE28 AH28 AK28 B29 E29 H29 M29 N29 P29 R29 U29 AA29 B30 E30 G30 U30 V30 Y30 AA30 AC30 AE30 AG30 AL30 F31 J31 M31 N31 P31 R31 T31 U31 AA31 AJ31 AM31 C32 E32 H32 U32 AA32 AC32 AE32 AG32 AK32 G33 R33 V33 Y33 AH33
MICRO-STAR INT'L CO.,LTD
Document Description
MCH_945GMS (DDR)
Rev 0A 7 of 40
Date: Monday, March 10, 2008
HA#[3..31]
HA#[3..31]
3 HD#[0..63]
BI HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 C4 F6 H9 H6 F7 E3 C2 C3 K9 F5 J7 K7 H8 E5 K8 J8 J2 J3 N1 M5 K5 J5 H3 J4 N3 M4 M3 N8 N6 K3 N9 M1 V8 V9 R6 T8 R2 N5 N2 R5 U7 R8 T4 T7 R3 T5 V6 V3 W2 W1 V2 W4 W7 W5 V5 AB4 AB8 W8 AA9 AA8 AB1 AB7 AA2 AB5
U26A H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF0 H_BNR# H_BPRI# H_BREQ0# H_CPURST# H_VREF1 HCLKN HCLKP H_DBSY# H_DEFER# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DPWR# H_DRDY# H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 F8 D12 C13 A8 E13 E12 J12 B13 A13 G13 A12 D14 F14 J13 E17 H15 G15 G14 A15 B18 B15 E14 H13 C14 A17 E15 H17 D17 G17 HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 BI H_ADS# F10 HASTB#0 C12 HASTB#1 H16 E2 H_BNR# B9 BI H_BPRI# OUT C7 G8 H_BR#0 BI B10 H_CPURST# OUT E1 AA6 AA5 C10 C6 H5 J6 T9 U6 G7 E6 F3 M8 T1 AA3 F4 M7 T2 AB3 CK_H_MCH CK_H_MCH# H_DBSY# BI H_DEFER# OUT DBI#0 DBI#1 DBI#2 DBI#3 H_DPWR# H_DRDY# HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 BI H_ADS# 3 3 U26G W33 AM33 AL33 C33 B33 AN32 A32 AN31 W28 V27 W29 J24 H24 W32 G24 F24 E24 D24 K33 A31 E21 C23 AN19 AM19 AL19 AK19 AJ19 AH19 AN3 Y9 J19 H19 G19 F19 E19 D19 C19 B19 A19 Y8 G16 F16 E16 D16 C16 B16 AN2 A16 Y7 AM4 AF4 AD4 AL4 AK4 W31 AJ4 AH4 AG4 AE4 AM1 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39 NC40 NC41 NC42 NC43 NC44 NC45 NC46 NC47 NC48 NC49 NC50 NC51 NC52 NC53 NC54 NC55 NC56 NC57 NC58 NC59 NC60 NC61 NC62 NC63 NC64 NC65 NC66 NC67 NC68 NC69 NC70 NC71 NC72 W30 Y6 AL1 Y5 Y10 W10 W25 V24 U24 V10 U10 K18
0.3125 * VTT Trace wide/spacing=10/20
V_FSB_VTT V_FSB_VTT
R341 221_1% HXSWING R343 100_1%
R338 221_1% HYSWING R340 100_1%
C359 0.1u_10V
C360 0.1u_10V
HVREF H_BNR# 3 H_BPRI# 3 H_BR#0 3 H_CPURST# 3 C365 R344 0.1u_16V 200_1%
IN CK_H_MCH 12 IN CK_H_MCH# 12 H_DBSY# 3 BI DBI#[0..3] H_DEFER# 3
HASTB#[0..1]
as close as to GMCH J13 pin
Trace wide/spacing=10/20
HXRCOMP R342 24.9_1%
HYRCOMP R339 24.9_1%
IN H_DPWR# 3 BI H_DRDY# 3 BI HDSTBN#0 3 BI HDSTBN#1 3 BI HDSTBN#2 3 BI HDSTBN#3 3 BI HDSTBP#0 3 BI HDSTBP#1 3 BI HDSTBP#2 3 BI HDSTBP#3 3
RESERVED26 RESERVED27 RESERVED28 RESERVED29 RESERVED30 RESERVED31 RESERVED32 RESERVED33 RESERVED34 RESERVED35 RESERVED36 RESERVED37 RESERVED38 RESERVED39 RESERVED40 RESERVED41 RESERVED42
Y25 Y24 AB22 AB21 AB19 AB16 AB14 AA12 W24 AA24 AB24 AB20 AB18 AB15 AB13 AB12 AB17
R440 54.9_1%
R349 54.9_1% HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING A10 A6 C15 J1 K1 H1
H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING
H_HIT# H_HITM# H_LOCK# H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_RS#_0 H_RS#_1 H_RS#_2 H_SLPCPU# H_TRDY#
C8 B4 C5 G9 E9 G12 B8 F12 A5 B6 G10 E8 E10
H_HIT# H_HITM# H_LOCK# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 RS#0 RS#1 RS#2 CPUSLP# H_TRDY#
H_HIT# H_HITM# H_LOCK#
HREQ#[0..4]
OUT OUT OUT OUT CPUSLP# 3 OUT
RS#0 RS#1 RS#2 H_TRDY#
945GMS 945GMS
MICRO-STAR INT'L CO.,LTD
Document Description
MCH_945GMS (HOST)
Rev 0A 8 of 40
Date: Monday, March 10, 2008
V_FSB_VTT H_DPRSTP# H_DPSLP# C621 15p_50V R674 VBAT 10M R667 330K_ X_0_p_50V VBAT R660 1M INTRUDER# Y5 INTVRMEN W4 EE_EECS EE_SHCLK EE_DOUT EE_DIN W1 Y1 Y2 W3 Y1 RTCX1 AB1 AB2 RTCX2 RTC_RST# AA3 32.768KHZ U47A RTXC1 RTCX2 RTCRST# INTRUDER# INTVRMEN EE_CS EE_SHCLK EE_DOUT EE_DIN LAN_CLK LAN_RSTSYNC LAD0 LAD1 LAD2 LAD3 AA6 AB5 AC4 Y6 AC3 AA5 AB3 AE22 AH28 AG27 AF24 AH25 AG26 AG24 AG22 AG21 AF22 AF25 AG23 AH24 AF23 AH22 AF26 AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15 AH17 AE17 AF17 AE16 AD16 R568 R567 0 0 IN OUT OUT OUT OUT OUT IN OUT OUT OUT OUT OUT H_A20M# IN OUT L_LDRQ1# T22 BI BI BI BI IN LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 13,29,31 13,29,31 13,29,31 13,29,31 U47B LPC_DRQ#0 13 32 LPC_FRAME# A20GATE H_A20M# TP27 H_DPRSTP# 3,22 H_DPSLP# 3 3 3 13 3 13,29,31 AD[31..0] BI AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10 E9 D9 B9 A8 A6 C7 B6 E6 D6 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 REQ0# GNT0# REQ1# GNT1# REQ2# GNT2# REQ3# GNT3# REQ4#/GPIO22 GNT4#/GPIO48 GPIO1/REQ5# GPIO17/GNT5# C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# D7 E7 C16 D16 C17 D17 E13 F13 A13 A14 C8 D8 B15 C12 D12 C15 A7 E10 B18 A12 C9 E11 B10 F15 F14 F16 C26 PLTRST# A9 B19 PREQ#0 PGNT#0 IN OUT PREQ#0 PGNT#0 32 32 R357 R355 1K/4 1K/4
LDRQ0# LDRQ1#/GPIO23 LFRAME# A20GATE A20M# CPUSLP# TP1/DPRSTP# TP2/DPSLP#
30 EE_EECS 30 EE_SHCLK 30 EE_DOUT 30 EE_DIN 30 EDGE_CONN_CLK 30 LAN_RSTSYNC 30 30 30 LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
BI BI BI BI BI BI IN IN IN OUT OUT OUT
EDGE_CONN_CLK V3 LAN_RSTSYNCU3 LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 U5 V4 T5 U7 V6 V7 U1 R6 R5 T2 T3 T1 T4
[GNT5# : GNT4#]= 0 : 1 || SPI SETTING
R256 100 C_BE#0 C_BE#1 C_BE#2 C_BE#3 BI BI OUT BI BI BI BI BI BI BI IN BI C_BE#[3..0] 32
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 ACZ_BCLK ACZ_SYNC ACZ_RST# ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2 ACZ_SDOUT SATALED# SATA0RXN SATA0RXP SATA0TXN SATA0TXP
FERR# GPIO49/CPUPWRGD
CPU_PWRGD H_IGNNE# 3 FWH_INIT 31 H_INIT# 3 H_INTR 3 KBRST# 13
AC-97/AZALIA
IGNNE# INT3_3V# INIT# INTR RCIN# NMI SMI# STPCLK# THERMTRIP# DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DA0 DA1 DA2 DCS1# DCS3#
Please R558 within 2& from ICH7R
V_FSB_VTT R558 R563 56 56 TRMTRIP# H_FERR#
ICH7-M PARTB
H_NMI 3 ICH_H_SMI# 3 H_STPCLK# IN 3 TRMTRIP# BI 3,6
TRMTRIP# PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 OUT OUT OUT OUT OUT
Please R559 within 2& from ICH7R
IRDY# 32 PAR 32 PCIRST_ICH7# DEVSEL# 32 PERR# 32 LOCK# 32 SERR# 32 STOP# 32 TRDY# 32 FRAME# 32 ICH_PCLK 12
10,18 SATALED# 20 20 20 20 20 20 20 20 SATA_RX#0 SATA_RX0 SATA_TX#0 SATA_TX0 SATA_RX#2 SATA_RX2 SATA_TX#2 SATA_TX2
OUT IN IN OUT OUT IN IN OUT OUT IN IN R358 24.9R1%4 SATAR_BIAS
AF18 AF3 AE3 AG2 AH2 AF7 AE7 AG6 AH6 AF1 AE1 AH10 AG10 AF15 AH15 AF16 AH16 AG16 AE15
PDD[0..15]
SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA_CLKN SATA_CLKP SATARBIASN SATARBIASP DIOR# DIOW# DDACK# IDEIRQ IORDY DDREQ
32 32 32 32
PIRQ#A PIRQ#B PIRQ#C PIRQ#D
BI BI BI BI
A3 B4 C5 B5
Interrupt I/F
PIRQA# PIRQB# PIRQC# PIRQD# GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#
G8 F7 F8 G7
BI BI BI BI
PIRQ#E PIRQ#F PIRQ#G PIRQ#H
32 32 32 32
12 CK_ICHSATA# 12 CK_ICHSATA
AE5 AD5 AG4 AH4 AD9 PD_A0 PD_A1 PD_A2 PD_CS#1 PD_CS#3 20 20 20 20 20 14 U920A
RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5]
RSVD[6] RSVD[7] RSVD[8] TP3 MCH_SYNC#
AE9 AG8 AH8 F21 AH20
TP32 BI MCH_ICH_SYNC#
INTEL-82801GBM-B0-RH VCC3 VCC3 14 U920B
20 PD_IOR# 20 PD_IOW# 20 PD_DACK# 20 IDE_IRQ 20 PD_IORDY 20 PD_DREQ
OUT OUT OUT IN IN IN
ICH7-M PARTA
INTEL-82801GBM-B0-RH
RN23 KBRST# A20GATE SATALED# 1 3 5 7 2 4 6 8 VCC3 PLTRST# 1
8.2K-8P4R VCC3_SB VBAT
VCC3 D23 1 BAT54C 3 R657 C597 1u_10V R664 1K VCC3 20K_1%_u_10V J_RTCRST# RTC_RST# CLR_CMOS0 3 3 2 2 1 1 H1X3_black
Modify from 24.9 ohm to 23.2 ohm
4 SN74LVC14APWR
PLTRST_EDGE#
SATAR_BIAS & 500mil
SN74LVC14APWR
6 SN74LVC14APWR
PLTRST_MS7#
8 SN74LVC14APWR
MICRO-STAR INT'L CO.,LTD
Document Description
ICH7M - CPU, LPC,SATA,Azalia
Rev 0A of 40
Date: Monday, March 10, 2008
VCC3 U47C 23 23 23 23 24 24 24 24 25 25 25 25 26 26 26 26 PCIE_RN0 PCIE_RP0 PCIE_TN0 PCIE_TP0 PCIE_RN1 PCIE_RP1 PCIE_TN1 PCIE_TP1 PCIE_RN2 PCIE_RP2 PCIE_TN2 PCIE_TP2 PCIE_RN3 PCIE_RP3 PCIE_TN3 PCIE_TP3 IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT IN IN OUT OUT F26 F25 E28 E27 H26 H25 G28 G27 K26 K25 J28 J27 M26 M25 L28 L27 P26 P25 N28 N27 T25 T24 R28 R27 31 31 SPI_CLK_F SPI_CS0_F# SPI_MOSI SPI_MISO IN IN 1 R643 2 10K 1 R646 2 10K BI BI SPI_CLK_F SPI_CS0_F# SPI_MOSI SPI_MISO R2 P6 P1 P5 P2 D3 C4 D5 D4 E5 C3 A2 B3
U47D PERn1 PERp1 PETn1 PETp1 PERn2 PERp2 PETn2 PETp2 DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP V26 V25 U28 U27 Y26 Y25 W28 W27 AB26 AB25 AA28 AA27 AD25 AD24 AC28 AC27 IN IN OUT OUT IN IN OUT OUT DMITXN0 DMITXP0 DMIRXN0 DMIRXP0 DMITXN1 DMITXP1 DMIRXN1 DMIRXP1 6 6 6 6 6 6 6 6
Clocks SATA GPIO
23,24,25,26,30,32 23,24,25,26,30,32
SMBCLK_RESUME SMBDATA_RESUME 3 LINK_ALERT# 3,32 SM_LINK0 3,32 SM_LINK1
BI BI BI IN IN
SMBCLK_RESUME SMBDATA_RESUME LINK_ALERT# SM_LINK0 SM_LINK1 RI#
C22 B22 A26 B25 A25 A28 A19 A27 A22
SMBCLK SMBDATA LINKALERT# SMLINK0 SMLINK1 RI# SPKR SUS_STAT# SYS_RST# GPIO0/BM_BUSY#
GPIO21/SATA0GP GPIO19/SATA1GP GPIO36/SATA2GP GPIO37/STAT3GP CLK14 CLK48 SUSCLK SLP_S3# SLP_S4# SLP_S5#
AF19 SATA0GP AH18 SATA1GP AH19 SATA2GP AE19 SATA3GP AC1 B2 C20 B24 D23 F22 AA4 AC22 C21 C23 C19 Y4 ICH7_LAN_RST# RSMRST_SB# PR0 0_0603 TP29 R562 X_0_0603
1 3 5 7 RN53 IN IN
2 4 6 8 8P4R-10K/4 ICH_14M USB_48 12 12
0.1u_10V 0.1u_10V
PCIE_TN0_C PCIE_TP0_C
0.1u_10V 0.1u_10V
PCIE_TN1_C PCIE_TP1_C
PCI-Express
18 12,13,18 6 23,24,25,26
SPKR FP_RST# IN IN
LPCPD# BM_BUSY# SMB_ALERT#
BM_BUSY# SMB_ALERT#
OUT OUT IN OUT
SLP_S3# 13,19,22 SLP_S4# 19 PWRGD 6,19,22 6,22
0.1u_10V 0.1u_10V
PCIE_TN2_C PCIE_TP2_C
PERn3 PERp3 PETn3 PETp3 PERn4 PERp4 PETn4 PETp4 PERn5 PERp5 PETn5 PETp5 PERn6 PERp6 PETn6 PETp6 SPI_CLK SPI_CS# SPI_ARB SPI_MOSI SPI_MISO
DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP DMI_ZCOMP DMI_IRCOMP USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBRBIAS# USBRBIAS
SYS GPIO Power MGT
GPIO11/SMBALERT# GPIO18/STPPCI# GPIO20/STPCPU# EL_RSVD/GPIO26 EL_STATE0/GPIO27 EL_STATE1/GPIO28 GPIO32/CLKRUN#
PWROK GPIO16/DPRSLPVR TP0/BATLOW# PWRBTN# LAN_RST# RSMRST#
0.1u_10V 0.1u_10V
PCIE_TN3_C PCIE_TP3_C
PM_STPPCI# AC20 PM_STPCPU# AF21 A21 30 CARD_GPIO1 30 CARD_GPIO2 BI BI CARD_GPIO1 CARD_GPIO2 B21 E23 AG18 RISER_GPI1 RISER_GPI2 23,24,25,26 13,31 12 22 VCC3 WAKE# SERIRQ THERM# VRM_GD IN BI IN IN WAKE# SERIRQ THERM# AC19 U2 F20 AH21 AF20 AD22 SIO_OVT# AC21 USER_GPIO6 AC18 GPIO8 E21
AE28 AE27 C25 D25 F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3 D2 D1 USB_BIAS R655 R557 24.9_1% IN IN CK_PE_100M_ICH# 12 CK_PE_100M_ICH 12 V_1P5_CORE USB0USB0+ USB1USB1+ USB2USB2+ USB3USB3+ 17 17 17 17 17 17 17 17
BATTLOW# IN PWRBTN# 13
GPIO33/AZ_DOCK_EN# GPIO34/AZ_DOCK_RST# WAKE# SERIRQ THRM# VRMPWRGD GPIO6 GPIO7 GPIO8
13 SIO_OVT# 20 USER_GPIO6
ICH7-M PARTC
GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15 GPIO24 GPIO25 GPIO35/STATCLKREQ# GPIO38 GPIO39
USER_GPIO1 E20 BI USER_GPIO1 20 USER_GPIO2 A20 BI USER_GPIO2 20 USER_GPIO3 F19 BI USER_GPIO3 20 E19 IN SIO_PME# 13 USER_GPIO4 R4 BI USER_GPIO4 20 GPIO15 E22 IN GPIO15 18 R3 EDGE_PRSNT2# IN EDGE_PRSNT2# 30 USER_GPIO5 D20 BI USER_GPIO5 20 AD21 USER_GPIO7 AD20 BI USER_GPIO7 20 USER_GPIO8 AE20 BI USER_GPIO8 20
31 17 17 OC#1 OC#2 VCC3_SB
CARD_GPIO1 CARD_GPIO2 PM_STPPCI# PM_STPCPU# RISER_GPI1 RISER_GPI2
R617 R619 R564 R572 R566 R571
X_4.7K X_4.7K 10K 10K 10K 10K
GPIO[0:15] --& SMI
INTEL-82801GBM-B0-RH
GPIO24 default low GPIO38 default low GPIO39 default low
LAN_RST# connect to PLTRST#. Follow Intel schematic checklist
OC0# OC1# OC2# OC3# OC4# OC5# / GPIO29 OC6# / GPIO30 OC7# / GPIO31
ICH7-M PARTD
BI BI BI BI BI BI BI BI
INTEL-82801GBM-B0-RH
22.6_1% USB_BIAS & 500mil
Strapping & Pull-up Resistor
RI# LINK_ALERT# SM_LINK0 SM_LINK1 SMB_ALERT# SIO_PME# BATTLOW# GPIO8 USER_GPIO1 USER_GPIO3 USER_GPIO4 LPCPD# WAKE# EDGE_PRSNT2# PM_STPPCI# PM_STPCPU# RISER_GPI1 RISER_GPI2 USER_GPIO5 2 4 6 8 2 4 6 8 2 4 6 8 R547 R574 R548 R549 R550 R554 R555 R559 1 3 5 7 1 3 5 7 1 3 5 7 10K 1K 10K 10K 10K 10K 10K 10K RSMRST# R698 X_0 RSMRST_SB# 3 D25 1 2 BAV99-7-F 19,23,24,25,26 RSMRST# IN ICH7_LAN_RST# R597 0 1 VCC3_SB RN17 8.2K-8P4R +12V
SM BUS ISOLATION
SMBDATA_RESUME
23,24,25,26,30,32
(To: PCI,PCI-Express,ICH7)
RN18 8.2K-8P4R VCC3_SB
Modify from Intel suggestion
Modify Rev-1A
Q35 N-2N7002
(To: CLK,DIMM,MS-7,HW_Monitor)
OUT SMBDATA_MAIN SMBCLK_RESUME 12,13,14,15,19,29 23,24,25,26,30,32
RN25 8.2K-8P4R
R665 4.7K Q51
19 SMB_PWROK
IN C525 OUT
(To: PCI,PCI-Express,ICH7)
0.1u_16V RSMRST_SB# R661 10K R603 1K Q37 N-2N7002
P-PMBS3906
(To: CLK,DIMM,MS-7, HW_Monitor)
OUT SMBCLK_MAIN 12,13,14,15,19,29
SMBCLK_MAIN SMBDATA_MAIN SMBCLK_RESUME SMBDATA_RESUME
R614 R591 4.7K R605 R598
3 PWRGD R662 10K R692 2.2K
D26 BAV99-7-F 2
9,18 SATALED#
SATALED# SERIRQ THERM# SIO_OVT# USER_GPIO6 USER_GPIO7 USER_GPIO8 SPKR
2 4 6 8 R601 R569 R570 R599
1 3 5 7 10K 10K 10K X_10K
VCC3 RN24 8.2K-8P4R
MICRO-STAR INT'L CO.,LTD
Reserved for No Reboot
Document Description
ICH7M - GPIO,PCIE,USB
Rev 0A 10 of 40
Date: Monday, March 10, 2008
U47F A4 A23 B1 B8 B11 B14 B17 B20 B26 B28 C2 C6 C27 D10 D13 D18 D21 D24 E1 E2 E4 E8 E15 F3 F4 F5 F12 F27 F28 G1 G2 G5 G6 G9 G14 G18 G21 G24 G25 G26 H3 H4 H5 H24 H27 H28 J1 J2 J5 J24 J25 J26 K24 K27 K28 L13 L15 L24 L25 L26 M3 M4 M5 M12 M13 M14 M15 M16 M17 M24 M27 M28 N1 N2 N5 N6 N11 N12 N13 N14 N15 N16 N17 N18 N24 N25 N26 P3 P4 P12 P13 P14 P15 P16 P17 P24 P27 VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] P28 R1 R11 R12 R13 R14 R15 R16 R17 R18 T6 T12 T13 T14 T15 T16 T17 U4 U12 U13 U14 U15 U16 U17 U24 U25 U26 V2 V13 V15 V24 V27 V28 W6 W24 W25 W26 Y3 Y24 Y27 Y28 AA1 AA24 AA25 AA26 AB4 AB6 AB11 AB14 AB16 AB19 AB21 AB24 AB27 AB28 AC2 AC5 AC9 AC11 AD1 AD3 AD4 AD7 AD8 AD11 AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21 AE24 AE25 AF2 AF4 AF8 AF11 AF27 AF28 AG1 AG3 AG7 AG11 AG14 AG17 AG20 AG25 AH1 AH3 AH7 AH12 AH23 AH27
5VREF Sequencing Circuit
5VREF D21 1N5817 5VREF C530 D22 1N5817 5VREF_SUS C562 0.1u_16V R634 0.1u_16V 10 AA22 AA23 AB22 AB23 AC23 AC24 AC25 AC26 AD26 AD27 AD28 D26 D27 D28 E24 E25 E26 F23 F24 G22 G23 H22 H23 J22 J23 K22 K23 L22 L23 M22 M23 N22 N23 P22 P23 R22 R23 R24 R25 R26 T22 T23 T26 T27 T28 U22 U23 V22 V23 W22 W23 Y22 Y23 B27 V_1P5_CORE AG28 AB7 AC6 AC7 AD6 AE6 AF5 AF6 AG5 AH5 AD2 C579 0.1u_16V VCC3 AH11 AB10 AB9 AC10 AD10 AE10 AF10 AF9 AG9 AH9 E3 VCC3_SB C602 0.1u_16V
V5REF[1] V5REF[2] V5REF_Sus Vcc1_5_B[1] Vcc1_5_B[2] Vcc1_5_B[3] Vcc1_5_B[4] Vcc1_5_B[5] Vcc1_5_B[6] Vcc1_5_B[7] Vcc1_5_B[8] Vcc1_5_B[9] Vcc1_5_B[10] Vcc1_5_B[11] Vcc1_5_B[12] Vcc1_5_B[13] Vcc1_5_B[14] Vcc1_5_B[15] Vcc1_5_B[16] Vcc1_5_B[17] Vcc1_5_B[18] Vcc1_5_B[19] Vcc1_5_B[20] Vcc1_5_B[21] Vcc1_5_B[22] Vcc1_5_B[23] Vcc1_5_B[24] Vcc1_5_B[25] Vcc1_5_B[26] Vcc1_5_B[27] Vcc1_5_B[28] Vcc1_5_B[29] Vcc1_5_B[30] Vcc1_5_B[31] Vcc1_5_B[32] Vcc1_5_B[33] Vcc1_5_B[34] Vcc1_5_B[35] Vcc1_5_B[36] Vcc1_5_B[37] Vcc1_5_B[38] Vcc1_5_B[39] Vcc1_5_B[40] Vcc1_5_B[41] Vcc1_5_B[42] Vcc1_5_B[43] Vcc1_5_B[44] Vcc1_5_B[45] Vcc1_5_B[46] Vcc1_5_B[47] Vcc1_5_B[48] Vcc1_5_B[49] Vcc1_5_B[50] Vcc1_5_B[51] Vcc1_5_B[52] Vcc1_5_B[53] Vcc3_3[1] VccDMIPLL[1] Vcc1_5_A[1] Vcc1_5_A[2] Vcc1_5_A[3] Vcc1_5_A[4] Vcc1_5_A[5] Vcc1_5_A[6] Vcc1_5_A[7] Vcc1_5_A[8] Vcc1_5_A[9] VccSATAPLL Vcc3_3[2] Vcc1_5_A[10] Vcc1_5_A[11] Vcc1_5_A[12] Vcc1_5_A[13] Vcc1_5_A[14] Vcc1_5_A[15] Vcc1_5_A[16] Vcc1_5_A[17] Vcc1_5_A[18] VccSus3_3[19] VccUSBPLL
Vcc1_05[1] Vcc1_05[2] Vcc1_05[3] Vcc1_05[4] Vcc1_05[5] Vcc1_05[6] Vcc1_05[7] Vcc1_05[8] Vcc1_05[9] Vcc1_05[10] Vcc1_05[11] Vcc1_05[12] Vcc1_05[13] Vcc1_05[14] Vcc1_05[15] Vcc1_05[16] Vcc1_05[17] Vcc1_05[18] Vcc1_05[19] Vcc1_05[20]
L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 V5 V1 W2 W7 U6 R7 AE23 AE26 AH26 AA7 AB12 AB20 AC16 AD13 AD18 AG12 AG15 AG19 A5 B13 B16 B7 C10 D15 F9 G11 G12 G16 W5 P7
V_FSB_VTT EC38 V 1 C555 0.1u_10V C543 1u_10V + 2
C601 0.1u_10V
Internal LAN power-off in S3-S5. Following Intel schematic checklist.
V_EXP_ICH V_1P5_CORE L24 EC37 V 80L3_100_u_25V 0.1u_25V 1
VccSus3_3/VccLAN3_3[1] VccSus3_3/VccLAN3_3[2] VccSus3_3/VccLAN3_3[3] VccSus3_3/VccLAN3_3[4] Vcc3_3/VccHDA
C607 0.1u_10V C599 0.1u_10V C498 0.1u_10V C494 C496
Near D28,T28,AD28
V_CPU_IO[1] V_CPU_IO[2] V_CPU_IO[3] Vcc3_3[3] Vcc3_3[4] Vcc3_3[5] Vcc3_3[6] Vcc3_3[7] Vcc3_3[8] Vcc3_3[9] Vcc3_3[10] Vcc3_3[11] Vcc3_3[12] Vcc3_3[13] Vcc3_3[14] Vcc3_3[15] Vcc3_3[16] Vcc3_3[17] Vcc3_3[18] Vcc3_3[19] Vcc3_3[20] Vcc3_3[21] VccRTC VccSus3_3[1] VccSus3_3[2] VccSus3_3[3] VccSus3_3[4] VccSus3_3[5] VccSus3_3[6] VccSus3_3[7] VccSus3_3[8] VccSus3_3[9] VccSus3_3[10] VccSus3_3[11] VccSus3_3[12] VccSus3_3[13] VccSus3_3[14] VccSus3_3[15] VccSus3_3[16] VccSus3_3[17] VccSus3_3[18] Vcc1_5_A[19] Vcc1_5_A[20]
4.7u_6.3V_0603
C529 0.1u_10V
C594 0.1u_10V
C606 0.1u_10V
C477 0.1u_16V
Near A5,B7,C10 C569 0.1u_10V 0.1u_10V C559 C581 0.1u_10V 0.1u_10V C609 0.1u_10V C608 0.1u_10V VBAT C578 VCC3
V_1P5_CORE R551 L26 1_1% 1u500m_ C463 0.01u_10V
10u_6.3V_0805
C600 A24 C24 D19 D22 G19 K3 K4 K5 K6 L1 L2 L3 L6 L7 M6 M7 N7 AB17 AC17 T7 F17 G17 AB8 AC8 K7 C28 G20 A1 H6 H7 J6 J7 C596 TP_VCCSUS1 TP_VCCSUS2 TP_VCCSUS3 0.1u_10V
C604 0.1u_10V
ICH7-M PART F
V_1P5_CORE L27 10u100mA_u_6.3V_0805
+ C648 near AH5
C490 0.1u_10V
VccSus3_3/VccSusHDA
0.1u_10V 0.1u_10V
C563 2.2u_10V_0805
C443 C450 0.1u_10V 1u_10V
V_1P5_CORE
C539 0.1u_16V V_1P5_CORE C557 1u_10V
Vcc1_5_A[21] Vcc1_5_A[22] Vcc1_5_A[23] Vcc1_5_A[24] Vcc1_5_A[25]
C1 AA2 V_1P5_CORE C595 0.1u_16V Y7
ICH7-M PARTE
VccSus1_05[1] VccSus1_05[2] VccSus1_05[3] Vcc1_5_A[26] Vcc1_5_A[27] Vcc1_5_A[28] Vcc1_5_A[29] Vcc1_5_A[30]
T25 T36 T26
VccSus1_05/VccLAN1_05[1] VccSus1_05/VccLAN1_05[2]
INTEL-82801GBM-B0-RH
INTEL-82801GBM-B0-RH
V_1P5_CORE
MICRO-STAR INT'L CO.,LTD
Document Description
ICH7M - POWER
Rev 0A 11 of 40
Date: Monday, March 10, 2008
Clock Generator VTT Power Down Block
Clock Generator - ICS954129
U42 43 CPU0 CPU0# CPU1 CPU1# CPU2_ITP/PCIEX5 CPU2_ITP#/PCIEX5# PCIEX0 PCIEX0# PCIEX1 PCIEX1# PCIEX2 PCIEX2# SRC SRC# PCIEX3 PCIEX3# PCIEX4 PCIEX4# DOT96 DOT96# VSSA VDDPCI GND VDDPCI GND VDD48 USB_48M **SEL24_48#/24_48MHz GND REF0/FSLC VDDREF X1 GND X2 SDATA SCLK 52 50 49 FSLA/PCICLK_F1 FSLB/PCICLK_F2 ITP_EN/PCICLK_F0 PCI0 ~PCI1 PCI2 PCICLK3 *Turbo# 8 9 7 54 55 2 3 6 12 11 45 44 42 41 36 35 17 18 21 22 23 24 26 27 31 30 33 32 14 15
Trace length less than 0.5inchs R498 R497 R496 R495 R421 R420 33 33 33 33 33 33 33 33 33 33 R493 R485 R534 R523 R476 R467 R460 R459 33 33 R427 R408 R428 R501 R502 R430 R409 USB48 SIO48 CLK_FSC PLL_XI PLL_XO R425 R426 R499 C421 Y0 14.318MHZ C413 IN IREF R527 33 33 33 51p_50V 51p_50V ITP_EN R389 10K CLK_EN# 475_1% 22 ICH_14M 33 33 33 33 33 33 33 33 33 CK_H_CPU CK_H_CPU# CK_H_MCH CK_H_MCH# CK_ICHSATA CK_ICHSATA# CK_PE_100M_MCH CK_PE_100M_MCH# CK_PE_100M_ICH CK_PE_100M_ICH# LAN1_100CLK_P LAN1_100CLK_N LAN0_100CLK_P LAN0_100CLK_N LAN2_100CLK_P LAN2_100CLK_N LAN3_100CLK_P LAN3_100CLK_N CK_96M_DREF CK_96M_DREF# 33 33 33 33 33 33
FB6 CB1 0.1u_16V
VCC3VB C402 0.1u_16V
VDDCPU GND VDDSRC VDDPCIE VDDPCIE
40 28 34 19
10u_6.3V_0805
CPUCLK CPUCLK# MCHCLK MCHCLK# CK_PE_SRC4 CK_PE_SRC4#
OUT OUT OUT OUT OUT OUT
CK_H_CPU 3 CK_H_CPU# 3 CK_H_MCH 8 CK_H_MCH# 8 CK_ICHSATA 9 CK_ICHSATA# 9 6 6 10 10 24 24 23 23 25 25 26 26
CK_H_CPU CK_H_CPU# CK_H_MCH CK_H_MCH# CK_PE_100M_ICH CK_PE_100M_ICH# CK_ICHSATA# CK_ICHSATA CK_PE_100M_MCH CK_PE_100M_MCH# CK_96M_DREF CK_96M_DREF# LAN3_100CLK_P LAN3_100CLK_N LAN2_100CLK_P LAN2_100CLK_N LAN1_100CLK_P LAN1_100CLK_N LAN0_100CLK_P LAN0_100CLK_N
R531 R530 R529 R528 R535 R537 R400 R401 R403 R402 R407 R406 R457 R452 R474 R466 R492 R484 R526 R521
49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1%
SIO_PCLK ICH_PCLK FWH_PCLK CPLD_33MHZ_CLK TPM_PCLK PCI_CLK0 USB_48
C378 C447 C392 C448 C366 C391 C375
X_10p25V X_10p25V X_10p25V X_10p25V X_10p25V X_10p25V 10p25V
0.1u_16V C431 0.1u_16V 0.1u_16V VCC3 FB5 CB0 0.1u_16V 80L3_100_ VCC3VA C430 0.1u_16V 37 38 56 C432 0.1u_16V 1 5 C440 0.1u_16V 4 10
C388 20 25 29 GND GND GND VDDA
CK_PE_SRC3 R432 CK_PE_SRC3# R431 CK_PE_SRC5 R513 CK_PE_SRC5# R512 LAN1_100CLK_P_R LAN1_100CLK_N_R LAN0_100CLK_P_R LAN0_100CLK_N_R LAN2_100CLK_P_R LAN2_100CLK_N_R LAN3_100CLK_P_R LAN3_100CLK_N_R CK_DOT96 CK_DOT96# CLK_FSA CLK_FSB ITP_EN PCICLK0 PCICLK1 PCICLK2 R424 R423
OUT CK_PE_100M_MCH OUT CK_PE_100M_MCH# OUT CK_PE_100M_ICH OUT CK_PE_100M_ICH# OUT LAN1_100CLK_P OUT LAN1_100CLK_N OUT LAN0_100CLK_P OUT LAN0_100CLK_N OUT LAN2_100CLK_P OUT LAN2_100CLK_N OUT LAN3_100CLK_P OUT LAN3_100CLK_N OUT OUT CK_96M_DREF 6 CK_96M_DREF# 6 OUT OUT OUT OUT OUT OUT SIO_PCLK 13 ICH_PCLK 9 FWH_PCLK 31 CPLD_33MHZ_CLK TPM_PCLK 31 PCI_CLK0 32 10 10 OUT R386 X_4.7K
ICH_14M SIO_48
X_10p25V 10p25V
PCI clock follow routing direction
EMC HF filter capacitors, located close to PLL
10u_6.3V_0805
SIO_PCLK ICH_PCLK FWH_PCLK PCI_CLK2 TPM_PCLK PCI_CLK0
THERM# USB_48
C390 0.1u_16V
C389 0.1u_16V SMBDATA_MAIN SMBCLK_MAIN R533 33 X_2.2K
10,13,14,15,19,29 10,13,14,15,19,29
SMBDATA_MAIN SMBCLK_MAIN
BI BI VCC3
Vtt_PwrGd#/PD IREF
(FSLC,FSLB,FSLA) ( 0 , 0 , 0 ) ( 0 , 0 , 1 ) ( 0 , 1 , 0 ) ( 0 , 1 , 1 ) ( 1 , 0 , 0 ) ( 1 , 0 , 1 ) ( 1 , 1 , 0 ) ( 1 , 1 , 1 )
CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00
PCIEX PCI MHz MHz 100.00 33.33 100.00 33.33 100.00 33.33 100.00 33.33 100.00 33.33 100.00 33.33 100.00 33.33 RESERVED
Reset# ICS954129BFLF
R388 1K 3,6 BSEL0 BI BSEL0 R387 1K 3,6 BSEL1 BI BSEL1 R532 1K 3,6 BSEL2 BI BSEL2 CLK_FSC CLK_FSB CLK_FSA
* Slave Address = 0XD2
MICRO-STAR INT'L CO.,LTD
Document Description
ICS954129 Gen
Rev 0A 12 of 40
Date: Monday, March 10, 2008
U3 6,19,31 DEV_RST# 12 SIO_PCLK 10,31 SERIRQ 9 LPC_DRQ#0 9,29,31 LPC_FRAME# 10 SIO_PME# VCC3 RN26 SPI_HOLD# SPI_WP# EN_BYPASS1# EN_BYPASS2# 2 4 6 8 1 3 5 7 9,29,31 LPC_AD[0..3] BI 30 21 23 22 29 86 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 27 26 25 24 LRESET# PCICLK SERIRQ LDRQ# LFRAME# PME# LAD0 LAD1 LAD2 LAD3 GP13/GPX2 GP15/GPY1 GP10/GPSA1 GP17/GPSA2 GP12/GPX1 GP14/GPY2 GP11/GPSB1 GP16/GPSB2 VREF AUXTIN CPUTIN SYSTIN RSTOUT1# RSTOUT0# VIN4 VIN3 VIN2 VIN1 VIN0 CPUVCORE VID5 VID4 VID3 VID2 VID1 VID0 DRVDEN0 INDEX# MOA# DSA# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# GP23/SCK OVT#/HM_SMI# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT PE BUSY ACK# SLIN# INIT# ERR# AFD# STB# GP34/RSTOUT4# GP36 GP35 GP55/SUSLED 1 3 4 6 8 9 10 11 13 14 15 16 17 2 5 42 41 40 39 38 37 36 35 31 32 33 34 43 44 45 46 47 88 69 87 70 56 50 53 51 54 49 52 57 84 79 82 80 83 78 81 85 59 60 63 62 66 65 118 75 71 20 55 19 117 BI BI DCDA# DSRA# SINA RTSA# SOUTA CTSA# DTRA# RIA# DCDB# DSRB# SINB RTSB# SOUTB CTSB# DTRB# RIB# A20GATE KBRST# 9 9 LAN_OFF2# LAN_OFF3# 25 26
SERIAL PORT 1
D0 U100 VCC5 NRIA# NDCDA# NDSRA# NSINA NCTSA# RTSA# SOUTA DTRA# SIO_OVT# 10 20 2 3 4 7 9 16 15 13 11 VCC RIN1 RIN2 RIN3 RIN4 RIN5 DIN1 DIN2 DIN3 GND V+ ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 DOUT1 DOUT2 DOUT3 V1 +12VC C9 0.1u_16V RIA# 19 DCDA# 18 DSRA# 17 SINA 14 CTSA# 12 NRTSA 5 NSOUTA 6 NDTRA 8 D3 1NVC C41 0.1u_16V 1N4148S +12V
SERIAL PORT 2
KBGND VCC5 11 NRIB# NDCDB# NDSRB# NSINB NCTSB# RTSB# SOUTB DTRB# 20 2 3 4 7 9 16 15 13 11
D1 U1 VCC RIN1 RIN2 RIN3 RIN4 RIN5 DIN1 DIN2 DIN3 GND V+ ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 DOUT1 DOUT2 DOUT3 V-
GPIO PULL-UP RESISTOR
1 +12VC C10 0.1u_16V RIB# 19 DCDB# 18 DSRB# 17 SINB 14 CTSB# 12 NRTSB 5 NSOUTB 6 NDTRB 8 D4 1NVC C40 0.1u_16V
8.2K-8P4R RN29 EN_WDTO_BYPASS2# EN_WDTO_RST# EXTSMI# EN_WDTO_BYPASS1# 2 4 6 8 1 3 5 7
SPI_HOLD# 125 31 SPI_HOLD# BI SPI_WP# 123 31 SPI_WP# BI EN_BYPASS1# 128 29 EN_BYPASS1# EN_BYPASS2# 121 29 EN_BYPASS2# EN_WDTO_BYPASS1# 126 29 EN_WDTO_BYPASS1# OUT EN_WDTO_BYPASS2# 124 29 EN_WDTO_BYPASS2# OUT EN_WDTO_RST# 127 29 EN_WDTO_RST# OUT EXTSMI# 122 29 EXTSMI# BI TMP_VREF AUX_TMP SYS_TMP N-2N7002 D G R36 4.7K S Q49 LPC_5VIN 2 1 R39 10K 2 1 R46 10K 101 102 103 104 93 94 95 96 97 98 99 100 105 106 107 108 109 110 112 115 119 120 113 116 111 58 7 CHASSIS S2DA1 S2CK1 76 89 90 91 92 64 67 68 72 73 18 61 74 VCC3 C8 Cu_16V X_C100p50N.1u_16V WDTO# 28 12 48 77 114
GD75232_SSOP20
NCTSA# NDTRA NSINA NSOUTA NRTSA NDSRA# NDCDA# NRIA#
1 3 5 7 1 3 5 7
2 4 6 8 2 4 6 8
NDCDA# NDSRA# NSINA NRTSA NSOUTA NCTSA# NDTRA NRIA#
1 6 2 7 3 8 4 9 5
GD75232_SSOP20
CN4 220p_8P4C 10
NCTSB# NDTRB NSINB NSOUTB NRTSB NDSRB# NDCDB# NRIB#
1 3 5 7 1 3 5 7
2 4 6 8 2 4 6 8
CN3 220p_8P4C NDCDB# NSOUTB CN1 220p_8P4C NRTSB NRIB#
1 3 5 7 9 2 NSINB 4 NDTRB 6 NDSRB# 8 NCTSB#
VCC_DDR2 VCC5 V_1P5_CORE VCORE
CN2 220p_8P4C KBGND KBGND
LPC_+12VIN
BH2X5(10)COM_black
CPUFANOUT0, AUXFANOUT are default PWM mode
TMP_VREF TMP_VREF R52 10K_1% AUX_TMP RT0 10KRT_1%_0805 AGND TMP_VREF R57 15K_1% CPU_TMPA C74 03 AGND R58 10K_1% SYS_TMP RT3 10KRT_1%_0805 AGND
+12V VCC5 R42 56K_1% R60 10K C1354 AGND FB4 X_C100p50N0402 CP4 CP2 CP1 X_COPPER X_COPPER KBGND KBGND X_0_0603 X_COPPER LPC_+12VIN
CPUFANOUT0, CPUFANOUT1 support SmartFAN III
21 CPU_FAN 21 CPUFAN_PWM 21 SYS_FAN 21 SYSFAN_PWM 21 AUX_FAN 21 AUXFAN_PWM BI 10,12,14,15,19,29 SMBDATA_MAIN BI 10,12,14,15,19,29 SMBCLK_MAIN 24 LAN_OFF1# 23 LAN_OFF0# R31 R33 BI BI PWRBTN# OUT PS_ON#
R62 R63 R59 R64 10 10
0 0 X_0 X_0
GP61/DCDA# CPUFANIN0 GP66/DSRA# CPUFANOUT0 GP63/SINA CPUFANIN1/GP21/MSI GP65/HEFRAS/RTSA# CPUFANOUT1/GP20/MSO GP62/PENKBC/SOUTA SYSFANIN GP67/CTSA# SYSFANOUT GP64/PENROM/DTRA# AUXFANIN0 GP60/RIA# AUXFANIN1/SO AUXFANOUT GP41/DCDB# GP46/DSRB# CASEOPEN# GP43/IRRX/SINB RSTOUT3#/GP33/SDA GP45/RTSB# RSTOUT2#/GP32/SCL GP42/IRTX/SOUTB GP31 GP47/CTSB# GP30 GP44/DTRB# GP37 GP40/RIB# PSOUT#/GP57 PSIN/GP56 PSON#/GP53 SUSB#/GP52 IOCLK 3VSB VBAT 3VCC 3VCC 3VCC EN_VRM10/WDTO#/GP50 AVCC W83627EHG-H GA20M KBRST GP26/KDAT GP27/KCLK GP24/MDAT GP25/MCLK SI/BEEP GP51/RSMRST# GP54/PWROK GND GND GP22/SCE# AGND
C1355 R40 X_C100p50N0402
LPC_5VIN 22K R37 10K
NOTE: LOCATE CLOSE STATUS PANEL
NOTE: LOCATE CLOSE SOUTH BRIDGE
10 PWRBTN# 18 PWRBTIN 18 PS_ON# 10,19,22 SLP_S3# 12 SIO_48
PS2 KEYBOARD & MOUSE CONNECTOR
2 4 6 8 RN0 1K-8P4R 1 3 5 7 KBDAT# KBCLK# FB1 FB0 FB3 FB2 120_3 120_3 KBDAT_PH# KBCLK_PH# C4 0.1u_16V MSDAT_PH# MSCLK_PH# 1 3 5 7 R3 X_1K 1.1A-microSMD110-S POLY SWITCH KBMS_Power
VCC3_SB VBAT
KBDAT# KBCLK# MSDAT# MSCLK# BEEP
FS0 J0 KBMS_Power 1 1 5 7 9 D2x5-BK 5 MSCLK_PH# 7 MSDAT_PH# 9 2 4 6 8 10 2 4 6 8 KBCLK_PH# 10 KBDAT_PH#
MSDAT# MSCLK#
CN0 VCC3 CP5 2 4 6 8 X_COPPER C75 0.1u_16V 220p_8P4C
LPC I/O STRAPPING RESISTOR
48MHz VCC3 R29 R8 R4 R7 X_1K 1K 4.7K 4.7K SOUTB VCC3 R5 R6 X_4.7K 1K SOUTA
Chasiss Intrusion
VCC5 VBAT R61 4.7K R76 X_4.7K OUT OUT CHASSIS 32 C BEEP R72 4.7K C B E ALARM 18 +12V VCC5
SMBus Conn
J7 VCC5 S2CK1 S2DA1 1 2 3 4 5 6
RTSA# DTRA# VCC3_SB
Disable KBC
JCI1 1 2 1 2
R18 1M CHASSIS
Q11 N-MMBT3904
X_H1X2_black R22 4.7K R19 EN_VRM10 X_1K R69 X_4.7K B E
Disable SPI
C1356 PWRBTN# X_C100p50N0402 BH1X6H#_white-RH C1357 X_C100p50N0402
Q10 X_N-MMBT3904
SOUTA SOUTB RTSA# DTRA# EN_VRM10
L: Disable KBC L: 24MHZ L: CFAD=2E L: Disable SPI L: TTL Level
H: Enable KBC H: 48MHZ H: CFAD=4E H: Enable SPI L: VRM10 Level
FP_RST# R704 0
VCC5 VBAT C470 0.1u_16V C514 C38 0.1u_16V C593 X_C0.1u_16V X_0.1u_16V
Ver C: POP R69, Q10, R76, R61 NOPOP R72 Ver G,H: POP R61, R72 NOPOP R69,Q10,R76
MICRO-STAR INT'L CO.,LTD
Document Description
LPC I/O - W83627EHG-H
Rev 0A 13 of 40
Date: Monday, March 10, 2008
7,15 DATA_A[0..63] DATA_A0 DATA_A1 DATA_A2 DATA_A3 DATA_A4 DATA_A5 DATA_A6 DATA_A7 DATA_A8 DATA_A9 DATA_A10 DATA_A11 DATA_A12 DATA_A13 DATA_A14 DATA_A15 DATA_A16 DATA_A17 DATA_A18 DATA_A19 DATA_A20 DATA_A21 DATA_A22 DATA_A23 DATA_A24 DATA_A25 DATA_A26 DATA_A27 DATA_A28 DATA_A29 DATA_A30 DATA_A31 DATA_A32 DATA_A33 DATA_A34 DATA_A35 DATA_A36 DATA_A37 DATA_A38 DATA_A39 DATA_A40 DATA_A41 DATA_A42 DATA_A43 DATA_A44 DATA_A45 DATA_A46 DATA_A47 DATA_A48 DATA_A49 DATA_A50 DATA_A51 DATA_A52 DATA_A53 DATA_A54 DATA_A55 DATA_A56 DATA_A57 DATA_A58 DATA_A59 DATA_A60 DATA_A61 DATA_A62 DATA_A63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
SO-DIMM0A DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DIMM-200S_black-1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 MAA_A0 MAA_A1 MAA_A2 MAA_A3 MAA_A4 MAA_A5 MAA_A6 MAA_A7 MAA_A8 MAA_A9 MAA_A10 MAA_A11 MAA_A12 MAA_A13 SBS_A2 SBS_A0 SBS_A1 SCS_A#0 SCS_A#1
MAA_A[0..13]
VCC_DDR2 SO-DIMM0B 112 111 117 96 95 118 81 82 87 103 88 104 CT34 0.1u10X4 199 83 120 50 69 163 203 204 1 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDDSPD NC1 NC2 NC3 NC4 NCTEST NC5 NC6 VREF VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
SMBCLK_MAIN SMBDATA_MAIN
SMBCLK_MAIN 10,12,13,15,19,29 SMBDATA_MAIN 10,12,13,15,19,29 VCC3
SCKE_A0 SCKE_A1 CAS_A# RAS_A# WE_A# SA_SA0 SA_SA1 SMBCLK_MAIN SMBDATA_MAIN ODT_A0 ODT_A1 BI BI BI BI BI BI BI BI
SBS_A0 7,16 SBS_A1 7,16 BI SCS_A#0 6,16 BI SCS_A#1 6,16 IN SM_CK_A1 6 IN SM_CK#_A1 6 IN SM_CK_A2 6 IN SM_CK#_A2 6 IN SCKE_A0 6,16 IN SCKE_A1 6,16 BI CAS_A# 7,16 BI RAS_A# 7,16 BI WE_A# 7,16
CT35 2.2u6.3Y6
CT27 X_0.01u16X4
R102 10K1%4 SMDDR_VREF SMDDR_VREF R103
PM_EXTTS#0
CT24 10K1%4 0.01u16X4 BI BI ODT_A0 ODT_A1 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 7,15 6,16 6,16
CT25 2.2u6.3Y6
CT23 0.1u10X4 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 DIMM-200S_black-1
DQM_A0 DQM_A1 DQM_A2 DQM_A3 DQM_A4 DQM_A5 DQM_A6 DQM_A7
DQS_A0 DQS_A1 DQS_A2 DQS_A3 DQS_A4 DQS_A5 DQS_A6 DQS_A7 DQS_A#0 DQS_A#1 DQS_A#2 DQS_A#3 DQS_A#4 DQS_A#5 DQS_A#6 DQS_A#7
ADDRESS: 00
SA_SA0 R290 10K/4
Layout note: Place capacitors between and near DDR connector if possible.
N13- Bottom
CT28 X_0.1u10X4
CT29 0.1u10X4
CT31 0.1u10X4
CT30 X_0.1u10X4
CT41 X_2.2u6.3Y6
CT32 2.2u6.3Y6
CT33 X_2.2u6.3Y6
CT42 2.2u6.3Y6
CT43 2.2u6.3Y6
MICRO-STAR INT'L CO.,LTD
Document Description
Rev 0A 14 of 40
Date: Monday, March 10, 2008
7,14 DATA_A[0..63] DATA_A0 DATA_A1 DATA_A2 DATA_A3 DATA_A4 DATA_A5 DATA_A6 DATA_A7 DATA_A8 DATA_A9 DATA_A10 DATA_A11 DATA_A12 DATA_A13 DATA_A14 DATA_A15 DATA_A16 DATA_A17 DATA_A18 DATA_A19 DATA_A20 DATA_A21 DATA_A22 DATA_A23 DATA_A24 DATA_A25 DATA_A26 DATA_A27 DATA_A28 DATA_A29 DATA_A30 DATA_A31 DATA_A32 DATA_A33 DATA_A34 DATA_A35 DATA_A36 DATA_A37 DATA_A38 DATA_A39 DATA_A40 DATA_A41 DATA_A42 DATA_A43 DATA_A44 DATA_A45 DATA_A46 DATA_A47 DATA_A48 DATA_A49 DATA_A50 DATA_A51 DATA_A52 DATA_A53 DATA_A54 DATA_A55 DATA_A56 DATA_A57 DATA_A58 DATA_A59 DATA_A60 DATA_A61 DATA_A62 DATA_A63 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
SO-DIMM1A DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DIMM-200S_black-1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16_BA2 BA0 BA1 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 107 106 110 115 30 32 164 166 79 80 113 108 109 198 200 197 195 114 119 10 26 52 67 130 147 170 185 13 31 51 70 131 148 169 188 11 29 49 68 129 146 167 186 MAA_B0 MAA_B1 MAA_B2 MAA_B3 MAA_B4 MAA_B5 MAA_B6 MAA_B7 MAA_B8 MAA_B9 MAA_B10 MAA_B11 MAA_B12 MAA_B13 SBS_B2 SBS_B0 SBS_B1 SCS_B#0 SCS_B#1
MAA_B[0..13]
VCC_DDR2 SO-DIMM1B 112 111 117 96 95 118 81 82 87 103 88 104 CT56 0.1u10X4 199 83 120 50 69 163 203 204 1 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDDSPD NC1 NC2 NC3 NC4 NCTEST NC5 NC6 VREF VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 18 24 41 53 42 54 59 65 60 66 127 139 128 145 165 171 172 177 187 178 190 9 21 33 155 34 132 144 156 168 2 3 15 27 39 149 161 28 40 138 150 162
SMBCLK_MAIN SMBDATA_MAIN
SMBCLK_MAIN 10,12,13,14,19,29 SMBDATA_MAIN 10,12,13,14,19,29 VCC3
SCKE_B0 SCKE_B1 CAS_B# RAS_B# WE_B# SA_SB0 SA_SB1 SMBCLK_MAIN SMBDATA_MAIN ODT_B0 ODT_B1 BI BI BI BI BI BI BI BI
SBS_B0 7,16 SBS_B1 7,16 BI SCS_B#0 6,16 BI SCS_B#1 6,16 IN SM_CK_B2 6 IN SM_CK#_B2 6 IN SM_CK_B1 6 IN SM_CK#_B1 6 IN SCKE_B0 6,16 IN SCKE_B1 6,16 BI CAS_B# 7,16 BI RAS_B# 7,16 BI WE_B# 7,16
CT55 2.2u6.3Y6
CT45 X_0.01u16X4
R104 10K1%4 SMDDR_VREF SMDDR_VREF R105
PM_EXTTS#0
CT51 10K1%4 0.01u16X4 BI BI ODT_B0 ODT_B1 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 7,14 6,16 6,16
CT57 2.2u6.3Y6
CT58 0.1u10X4 47 133 183 77 12 48 184 78 71 72 121 122 196 193 8 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 DIMM-200S_black-1
DQM_A0 DQM_A1 DQM_A2 DQM_A3 DQM_A4 DQM_A5 DQM_A6 DQM_A7
DQS_A0 DQS_A1 DQS_A2 DQS_A3 DQS_A4 DQS_A5 DQS_A6 DQS_A7 DQS_A#0 DQS_A#1 DQS_A#2 DQS_A#3 DQS_A#4 DQS_A#5 DQS_A#6 DQS_A#7
VCC3 SA_SB0 R302 10K/4
ADDRESS: 01 0xA2
Layout note: Place capacitors between and near DDR connector if possible.
N13- Bottom
CT46 X_0.1u10X4
CT47 0.1u10X4
CT48 0.1u10X4
CT50 X_0.1u10X4
CT44 X_2.2u6.3Y6
CT49 2.2u6.3Y6
CT52 X_2.2u6.3Y6
CT53 2.2u6.3Y6
CT54 2.2u6.3Y6
MICRO-STAR INT'L CO.,LTD
Document Description
Rev 0A 15 of 40
Date: Monday, March 10, 2008
RNT24 6,14 6,14 7,14 ODT_A1 SCS_A#1 WE_A# IN IN IN ODT_A1 WE_A# SBS_A0 8 6 4 2 7 5 3 1 56-8P4R 1 3 5 7
RNT23 2 4 6 8 56-8P4R RNT22 RAS_A# SBS_A1 ODT_A0 IN IN IN SCS_A#0 RAS_A# ODT_A0 6,14 7,14 6,14 RNT18 MAA_A10 MAA_A1 MAA_A5 MAA_A9 8 6 4 2 7 5 3 1 56-8P4R 7 5 3 1 RNT15 8 6 4 2 56-8P4R RNT16 2 4 6 8 56-8P4R RAS_B# MAA_B0 MAA_B4 MAA_B2 IN RAS_B# 7,15
MAA_A[0..13] SBS_A[0..2