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P R O D U C T O TSpartan-3E FPGA Family Data SheetDS312 October 29, 2012 Product SpecificationModule 1: N Introduction and Ordering InformationDS312 (4.0) October 29, 2012 ? Introduction ? Features R ? Architectural Overview E ? Package Marking C ? Ordering Information OModule 3: DC and Switching CharacteristicsDS312 (4.0) October 29, 2012 ? DC Electrical Characteristics ? ? ? ? ? ? ? ? ? ? ? Absolute Maximum Ratings Supply Voltage Specifications Recommended Operating Conditions DC Characteristics I/O Timing SLICE Timing DCM Timing Block RAM Timing Multiplier Timing Configuration and JTAG TimingM Module 2: M Functional Description E DS312 (4.0) October 29, 2012 N ? D E D? ? Input/Output Blocks (IOBs) ? ? Overview SelectIO? Signal StandardsSwitching CharacteristicsConfigurable Logic Block (CLB) Block RAM Dedicated Multipliers Digital Clock Manager (DCM) Clock NetworkF ? O ? R?Module 4: Pinout DescriptionsDS312 (4.0) October 29, 2012 ? ? ? ? Pin Descriptions Package Overview Pinout Tables Footprint Diagrams? Configuration N ? Powering Spartan?-3E FPGAs EW? D E S I G N SProduction Stepping? Copyright
Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.w D 1 w S w 3P R O Spartan-3 FPGA Family: Introduction and Ordering D Information U C DS312 (4.0) October 29, 2012 Product T Specification N Introduction O The Spartan?-3E family of Field-Programmable Gate T Arrays (FPGAs) is specifically designed to meet the needsof high volume, cost-sensitive consumer electronic applications. The five-member family offers densities R ranging from 100,000 to 1.6 million system gates, as shown E in Table 1. The Spartan-3E family builds on the success of the earlier O Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features M improve system performance and reduce the cost of M configuration. These Spartan-3E FPGA enhancements, E combined with advanced 90 nm process technology, deliver N more functionality and bandwidth per dollar than was previously possible, setting new standards in the D programmable logic industry. E Because of their exceptionally low cost, Spartan-3E FPGAs D are ideally suited to a wide range of consumer electronics applications, including broadband access, home F networking, display/projection, and digital television O equipment.?C???R The Spartan-3E family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of N conventional ASICs. Also, FPGA programmability permits E design upgrades in the field with no hardware replacement W necessary, an impossibility with ASICs. D Features E ? Very low cost, high-performance logic solution for S high-volume, consumer-oriented applications ? I Proven advanced 90-nanometer process technology ? G Multi-voltage, multi-standard SelectIO? interface pins ? Up to 376 I/O pins or 156 differential signal pairs N Table 1: Summary of Spartan-3E FPGA Attributes SDevice System Equivalent Gates Logic Cells CLB Array (One CLB = Four Slices) Total Total Rows Columns CLBs Slices 22 16 240 960 34 26 612 2,448 46 34 1,164 4,656 60 46 2,168 8,672 76 58 3,688 14,752? ?? ? ? ? ? ? ?LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards ? 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling ? 622+ Mb/s data transfer rate per I/O ? True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O ? Enhanced Double Data Rate (DDR) support ? DDR SDRAM support up to 333 Mb/s Abundant, flexible logic resources ? Densities up to 33,192 logic cells, including optional shift register or distributed RAM support ? Efficient wide multiplexers, wide logic ? Fast look-ahead carry logic ? Enhanced 18 x 18 multipliers with optional pipeline ? IEEE 2 JTAG programming/debug port Hierarchical SelectRAM? memory architecture ? Up to 648 Kbits of fast block RAM ? Up to 231 Kbits of efficient distributed RAM Up to eight Digital Clock Managers (DCMs) ? Clock skew elimination (delay locked loop) ? Frequency synthesis, multiplication, division ? High-resolution phase shifting ? Wide frequency range (5 MHz to over 300 MHz) Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing Configuration interface to industry-standard PROMs ? Low-cost, space-saving SPI serial Flash PROM ? x8 or x8/x16 parallel NOR Flash PROM ? Low-cost Xilinx? Platform Flash with JTAG Complete Xilinx ISE? and WebPACK? software MicroBlaze? and PicoBlaze? embedded processor cores Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in some devices) Low-cost QFP and BGA packaging options Common footprints support easy density migration Pb-free packaging options XA Automotive version availableDistributed RAM bits(1) 15K 38K 73K 136K 231KBlock RAM bits(1) 72K 216K 360K 504K 648KDedicated DCMs Multipliers 4 12 20 28 36 2 4 4 8 8Maximum User I/O 108 172 232 304 376Maximum Differential I/O Pairs 40 68 92 124 156XC3S100E 100K 2,160 XC3S250E 250K 5,508 XC3S500E 500K 10,476 XC3SK 19,512 XC3SK 33,192 Notes: 1. By convention, one Kb is equivalent to 1,024 bits.? Copyright
Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.2 w D w S w 3P R O Architectural Overview D U The Spartan-3E family architecture consists of five fundamental programmable functional elements: C ? Configurable Logic Blocks (CLBs) contain flexible T N O T ? R E C O ? M M ? E N D E D F O R N E W D E S I G N SS p a r t Figure 1: Spartan-3E Family Architecture a n 3 F P G A F Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product.?Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XC3S100E, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XC3S100E has only one DCM at the top and bottom, while the XC3S1200E and XC3S1600E add two DCMs in the middle of the left and right sides. The Spartan-3E family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing.3 w D w S w 3P R O Configuration D U Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static C CMOS configuration latches (CCLs) that collectively control T all functional elements and routing resources. The FPGA‘sconfiguration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After N applying power, the configuration data is written to the O FPGA using any of seven different modes: ?I/O CapabilitiesThe Spartan-3E FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Spartan-3E FPGAs support the following single-ended standards: ? ? 3.3V low-voltage TTL (LVTTL) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V ? ? ? 3V PCI at 33 MHz, and in some devices, 66 MHz HSTL I and III at 1.8V, commonly used in memory applications SSTL I at 1.8V and 2.5V, commonly used for memory applicationsTMaster Serial from a Xilinx Platform Flash PROM? Serial Peripheral Interface (SPI) from an R industry-standard SPI serial Flash ?E C Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16 parallel NOR Flash O Slave Serial, typically downloaded from a processor ? M ? Slave Parallel, typically downloaded from a processor M ? Boundary Scan (JTAG), typically downloaded from a E processor or system tester. N Furthermore, Spartan-3E FPGAs support MultiBoot D configuration, allowing two or more FPGA configuration E bitstreams to be stored in a single parallel NOR Flash. The FPGA application controls which configuration to load next Dand when to load it.Spartan-3E FPGAs support the following differential standards: ? ? ? ? ? ? ? LVDS Bus LVDS mini-LVDS RSDS Differential HSTL (1.8V, Types I and III) Differential SSTL (2.5V and 1.8V, Type I) 2.5V LVPECL inputsF O RTable 2: Available User I/Os and Differential (Diff) I/O PairsN E Package W FootprintVQ100 VQG100 16 x 16 User 66(2) 9(7) 66 (7) 66(3) (7) Diff 30 (2) 30 (2) 30 (2) -CP132 CPG132 8x8 User 83 (11) 92 (7) 92 (7) Diff 35 (2) 41 (2) 41 (2) -TQ144 TQG144 22 x 22 User 108 (28) 108 (28) Diff 40 (4) 40 (4) -PQ208 PQG208 30.5 x 30.5 User 158 (32) 158 (32) Diff 65 (5) 65 (5) -FT256 FTG256 17 x 17 User 172 (40) 190 (41) 190 Diff 68 (8) 77 (8) 77FG320 FGG320 19 x 19 User 232 (56) 250 Diff 92 (12) 99FG400 FGG400 21 x 21 User 304 Diff 124FG484 FGG484 23 x 23 User Diff -Size (mm) Device D E XC3S100E S IXC3S250E G XC3S500E N S XC3S1200E(40) (8) (56) (12) (72) (20) S p 250 99 304 124 376 156 XC3S1600E - a (56) (12) (72) (20) (82) (21) r Notes: t 1. All Spartan-3E devices provided in a same package are pin-compatible as further described in Module 4, Pinout Descriptions. the 2. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number n of input-only pins. 3. The XC3S500E is available in the VQG100 Pb-free package and not the standard VQ100. The VQG100 and VQ100 pin-outs are identical 3and general references to the VQ100 will apply to the XC3S500E.4 w D w S w 3F P G A FP R O Package Marking D U Figure 2 provides a top marking example for Spartan-3E FPGAs in the quad-flat packages. Figure 3 shows the top C marking for Spartan-3E FPGAs in BGA packages except T the 132-ball chip-scale package (CP132 and CPG132). Themarkings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is N rotated with respect to the ball A1 indicator. Figure 4 shows O the top marking for Spartan-3E FPGAs in the CP132 and T CPG132 packages.On the QFP and BGA packages, the optional numerical Stepping Code follows the Lot Code. The D5C‖ and D4I‖ part combinations can have a dual mark of D5C/4I‖. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. All D5C‖ and D4I‖ part combinations use the Stepping 1 production silicon.R Mask Revision Code E C O M M E N D E D F O R N E W D E S I G N SFabrication CodeR RSPARTATMProcess Technology Date Code Stepping Code (optional) Lot CodeDevice Type Package Speed Grade Temperature RangeN XC3S250EPQ208AGQ7A 4CPin P1DS312-1_06_102905Figure 2: Spartan-3E QFP Package Marking ExampleMask Revision Code BGA Ball A1 Device Type PackageRSPARTANRFabrication Code Process Code Date Code Stepping Code (optional) Lot CodeXC3S250ETM FT256AGQ7A 4CSpeed Grade Temperature RangeDS312-1_02_090105Figure 3: Spartan-3E BGA Package Marking ExampleBall A1 Lot Code3S250E F5 PHILIPPINESDevice Type Date Code Temperature RangeS Package C5AGQ 4C pC5 = CP132 aC6 = CPG132 Speed Grade Process Code r Mask Revision Code Fabrication Code t DS312-1_05_032105 a Figure 4: nSpartan-3E CP132 and CPG132 Package Marking Example 3 F P G A F5 w D w S w 3P R O Ordering Information D U Spartan-3E FPGAs are available in both standard and Pbfree packaging options for all device/package combinations. C All devices are available in Pb-free packages, which adds a T ?G‘ character to the ordering code. All devices are availablein either Commercial (C) or Industrial (I)temperature ranges. Both the standard C4 and faster C5 speed grades are available for the Commercial temperature range. However, only the C4 speed grade is available for the Industrial temperature range. See Table 2 for valid device/package combinations.N O T R E C Device O XC3S100E M XC3S250E M E XC3S500E(2) N D XC3S1200E E XC3S1600E D F O R N E 1. W 2.3.Example:Device Type Speed Grade Package TypeXC3S250E -4 FT 256 C S1 (optional code to specify Stepping 1)Temperature Range Number of PinsDS312_03_082409Speed Grade -4 Standard Performance VQ100 VQG100 -5 High Performance(1) CP132 CPG132 TQ144 TQG144 PQ208 PQG208 FT256 FTG256 FG320 FGG320 FG400 FGG400 FG484 FGG484Package Type / Number of Pins 100-pin Very Thin Quad Flat Pack (VQFP) 132-ball Chip-Scale Package (CSP) 144-pin Thin Quad Flat Pack (TQFP) 208-pin Plastic Quad Flat Pack (PQFP) 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) 320-ball Fine-Pitch Ball Grid Array (FBGA) 400-ball Fine-Pitch Ball Grid Array (FBGA) 484-ball Fine-Pitch Ball Grid Array (FBGA)Temperature Range ( TJ ) C Commercial (0° to 85° C C) I Industrial (C40° to 100° C C)Notes:The -5 speed grade is exclusively available in the Commercial temperature range. The XC3S500E VQG100 is available only in the -4 Speed Grade. See DS635 for the XA Automotive Spartan-3E FPGAs.D Production SteppingThe Spartan-3E FPGA family uses production stepping to S indicate improved capabilities or enhanced features. Stepping 1 is, by definition, a functional superset of G Stepping 0. Furthermore, configuration bitstreams generated for any stepping are forward compatible. See N Table 72 for additional details. S Xilinx has shipped both Stepping 0 S Stepping 1. Designs and p operating on the Stepping 0 devices perform similarly on a a Stepping 1 device. Stepping 1 devices have been shipping r since 2006. The faster speed grade (-5), Industrial (I grade), t Automotive devices, and -4C devices with date codes 0901 a (2009) and later, are always Stepping 1 devices. Only -4C devices have shipped as Steppingn devices. 0 To specify only the later stepping for the -4C, append an S# 3 suffix to the standard ordering code, where # is the stepping number, as indicated in Table 3. F P G A6 w D w S w 3E ITable 3: Spartan-3E Optional Stepping Level OrderingStepping Number 0 1 Suffix Code None or S0 S1 Status Production ProductionThe stepping level is optionally marked on the device using a single number character, as shown in Figure 2, Figure 3, and Figure 4.FP R O Revision History D U The following table shows the revision history for this document. C Version T Date03/01/05 1.0 1.1 Initial Xilinx release.RevisionN 03/21/05 O T 11/23/05 R 03/22/06 E C 11/09/06 O M 04/18/08 M 08/26/09 E N D E 10/29/12 DAdded XC3S250E in CP132 package to Table 2. Corrected number of differential I/O pairs for CP132 package. Added package markings for QFP packages (Figure 2) and CP132/CPG132 packages (Figure 4). Added differential HSTL and SSTL I/O standards. Updated Table 2 to indicate number of input-only pins. Added Production Stepping information, including example top marking diagrams. Upgraded data sheet status to Preliminary. Added XC3S100E in CP132 package and updated I/O counts for the XC3S1600E in FG320 package (Table 2). Added information about dual markings for C5C and C4I product combinations to Package Marking. Added 66 MHz PCI support and links to the Xilinx PCI LogiCORE data sheet. Indicated that Stepping 1 parts are Production status. Promoted Module 1 to Production status. Synchronized all modules to v3.4. Added XC3S500E VQG100 package. Added reference to XA Automotive version. Updated links. Added paragraph to Configuration indicating the device supports MultiBoot configuration. Added package sizes to Table 2. Described the speed grade and temperature range guarantee for devices having a single mark in paragraph 3 under Package Marking. Deleted Pb-Free Packaging example under Ordering Information. Revised information under Production Stepping. Revised description of Table 3. Added Notice of Disclaimer. This product is not recommended for new designs. Updated Table 2 footprint size of PQ208.2.0 3.03.43.7 3.84.0Notice of Disclaimer F O THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (DPRODUCTS‖) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED RWARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE N PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES E THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (DCRITICAL W APPLICATIONS‖). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER D XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE E FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE S DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE I PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, DCRITICAL APPLICATIONS‖). FURTHERMORE, G XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF N SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE S OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX S PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY p APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL a APPLICATIONS. AUTOMOTIVE APPLICATIONS DISCLAIMER t XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING a FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A n VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) 3 USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.r7 w D w S w 3F P G A FP R O Spartan-3 FPGA Family: Functional Description D U DS312 (4.0) October 29, 2012 Product C Specification T Design Documentation Available Xilinx Alerts N The functionality of the Spartan?-3E FPGA family is now Create a Xilinx user account and sign up to receive O described and updated in the following documents. The automatic e-mail notification whenever this data sheet or T topics covered in each guide are listed below. the associated user guides are updated.?R E C O M M E N D E D F O RUG331: Spartan-3 Generation FPGA User Guide ? ? ? ? Clocking Resources Digital Clock Managers (DCMs) Block RAM Configurable Logic Blocks (CLBs) ? ? ? ? ? ? ? ? ? ? Distributed RAM SRL16 Shift Registers Carry and Arithmetic LogicSign Up for Alerts on Xilinx.com https://secure.xilinx.com/webreg/register.do ?group=myprofile&languageID=1Spartan-3E FPGA Starter KitFor specific hardware examples, please see the Spartan-3E FPGA Starter Kit board web page, which has links to various design examples and the user guide. ? ? Spartan-3E FPGA Starter Kit Board page http://www.xilinx.com/s3estarter UG230: Spartan-3E FPGA Starter Kit User GuideI/O Resources Embedded Multiplier Blocks Programmable Interconnect ISE? Design Tools IP Cores Embedded Processing and Control Solutions Pin Types and Package Overview Package Drawings Powering FPGAs Power ManagementN E ? W D E S I G N SUG332: Spartan-3 Generation Configuration User Guide ? Configuration Overview ? ? ? Configuration Pins and Behavior Bitstream Sizes Master Serial Mode using Xilinx? Platform Flash PROM Master SPI Mode using Commodity SPI Serial Flash PROM Master BPI Mode using Commodity Parallel NOR Flash PROM Slave Parallel (SelectMAP) using a Processor Slave Serial using a Processor JTAG ModeDetailed Descriptions by ModeISE iMPACT Programming Examples MultiBoot Reconfiguration? Copyright
Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.8 w D w S w 3P R O Introduction D U As described in Architectural Overview, the Spartan-3E FPGA architecture consists of five fundamental functional C elements: T? Input/Output Blocks (IOBs) ? Configurable Logic Block (CLB) and Slice Resources N ? Block RAM O ? Dedicated Multipliers T ? Digital Clock Managers (DCMs)pair of storage elements to the IQ1 and IQ2 lines. The IOB outputs I, IQ1, and IQ2 lead to the FPGA‘s internal logic. The delay element can be set to ensure a hold time of zero (see Input Delay Functions). ? The output path, starting with the O1 and O2 lines, carries data from the FPGA‘s internal logic through a multiplexer and then a three-state driver to the IOB pad. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. The 3-state path determines when the output driver is high impedance. The T1 and T2 lines carry data from the FPGA‘s internal logic through a multiplexer to the output driver. In addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. All signal paths entering the IOB, including those associated with the storage elements, have an inverter option. Any inverter placed on these paths is automatically absorbed into the IOB.?R The following sections provide detailed information on each of these functions. In addition, this section also describes E the following functions: C? Clocking Infrastructure O ? Interconnect M ? Configuration M ?E ? Powering Spartan-3E FPGAs N D Input/Output Blocks (IOBs) E For additional information, refer to the DUsing I/O D Resources‖ chapter in UG331.IOB Overview FO The Input/Output Block (IOB) provides a programmable, R unidirectional or bidirectional interface between a package pin and the FPGA‘s internal logic. The IOB is similar to that of the Spartan-3 family with the following differences:? Input-only blocks are added E ? Programmable input delays are added to all blocks W ? DDR flip-flops can be shared between adjacent IOBsND The unidirectional input-only block has a subset of the full IOB capabilities. Thus there are no connections or logic for E an output path. The following paragraphs assume that any S reference to output functionality does not apply to the I input-only blocks. The number of input-only blocks varies with device size, but is never more than 25% of the total IOB G count. NFigure 5 is a simplified diagram of the IOB‘s internal S structure. There are three main signal paths within the IOB: S the output path, input path, and 3-state path. Each path has p its own pair of storage elements that can act as either a registers or latches. For more information, see Storage r t Element Functions. The three main signal paths are as a follows: n ? The input path carries data from the pad, which is bonded to a package pin, through an optional 3 programmable delay element directly to the I line. After the delay element, there are alternate routes through a F P G A9 w D w S w 3FP R O DT U C T1 T N O T R E C O M M E N D E D F O R N E W D E S I G N SI IQ1 IDDRIN1 IDDRIN2 ICLK1 ICE IQ2TCE T2D CE Q CK SR REVTFF1DDR MUX D CE CK SR REVThree-state PathQ TFF2O1 OTCLK1D CE CK SRQOFF1VCCOPull-Up REVDDR MUXESDI/O PinOCE O2 OTCLK2 D CE CK SR REV Q OFF2Programmable Output DriverPullDownESDKeeper LatchOutput Path Programmable Delay Programmable Delay D CE CK SR REV Q IFF1LVCMOS, LVTTL, PCISingle-ended Standards using VREF VREF Pin Differential Standards I/O Pin from Adjacent IOBD CE ICLK2 SR REV CK SRQ IFF2REVS p a Input Path r t Figure a Simplified IOB Diagram 5: n 3 F P G A FDS312-2_19_1106061 w D 0 w S w 3P R O Input Delay Functions D Each IOB has a programmable delay block that optionally U delays the input signal. In Figure 6, the signal path has a C coarse delay element that can be bypassed. The input T signal then feeds a 6-tap delay line. The coarse and tap refer to timing reports for specific delay values. All six taps are available via a multiplexer for use as an N asynchronous input directly into the FPGA fabric. In this O way, the delay is programmable in 12 steps. Three of the six T taps are also available via a multiplexer to the D inputs of the synchronous storage elements. The delay inserted in the path to the storage element can be varied in six steps. R The first, coarse delay element is common to both E asynchronous and synchronous paths, and must be either C used or not used for both paths. The delay values are set up in the silicon once at M configuration time―they are non-modifiable in device operation. Mreport generated by the implementation tools, and the resulting effects on input timing are reported using the Timing Analyzer tool. If the design uses a DCM in the clock path, then the delay element can be safely set to zero because the Delay-Locked Loop (DLL) compensation automatically ensures that there is still no input hold time requirement. Both asynchronous and synchronous values can be modified, which is useful where extra delay is required on clock or data inputs, for example, in interfaces to various types of RAM. These delay values are defined through the IBUF_DELAY_VALUE and the IFD_DELAY_VALUE parameters. The default IBUF_DELAY_VALUE is 0, bypassing the delay elements for the asynchronous input. The user can set this parameter to 0-12. The default IFD_DELAY_VALUE is AUTO. IBUF_DELAY_VALUE and IFD_DELAY_VALUE are independent for each input. If the same input pin uses both registered and non-registered input paths, both parameters can be used, but they must both be in the same half of the total delay (both either bypassing or using the coarse delay element).OE The primary use for the input delay element is to adjust the input delay path to ensure that there is no hold time N requirement when using the input flip-flop(s) with a global D clock. The default value is chosen automatically by the E Xilinx software tools as the value depends on device size D and the specific device edge where the flip-flop resides. The value set by the Xilinx ISE software is indicated in the Map F O R N E W D E S I G N SIFD_DELAY_VALUE Synchronous input (IQ1)D Q Synchronous input (IQ2) D QCoarse DelayPADAsynchronous input (I) IBUF_DELAY_VALUEUG331_c10_09_011508Figure 6: Programmable Fixed Input Delay Elements S p a r t a n 3 F P G A F1 w D 1 w S w 3P R O Storage Element Functions D There are three pairs of storage elements in each IOB, one U pair for each of the three paths. It is possible to configure C each of these storage elements as an edge-triggered T D-type flip-flop (FD) or a level-sensitive latch (LD).The storage-element pair on either the Output path or the N Three-State path can be used together with a special O multiplexer to produce Double-Data-Rate (DDR) transmission. This is accomplished by taking data T Table 4: Storage Element Signal Descriptionsynchronized to the clock signal‘s rising edge and converting it to bits synchronized on both the rising and the falling edge. The combination of two registers and a multiplexer is referred to as a Double-Data-Rate D-type flip-flop (ODDR2). Table 4 describes the signal paths associated with the storage element.RStorage EElement C Signal D O M Q M E CK N CE D SR E DREVDescription Data input Data output Clock input Clock Enable input Set/Reset inputFunction Data at this input is stored on the active edge of CK and enabled by CE. For latch operation when the input is enabled, data passes directly to the output Q. The data on this output reflects the state of the storage element. For operation as a latch in transparent mode, Q mirrors the data at D. Data is loaded into the storage element on this input‘s active edge with CE asserted. When asserted, this input enables CK. If not connected, CE defaults to the asserted state. This input forces the storage element into the state specified by the SRHIGH/SRLOW attributes. The SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not. If both SR and REV are active at the same time, the storage element gets a value of 0. This input is used together with SR. It forces the storage element into the state opposite from what SR does. The SYNC/ASYNC attribute setting determines whether the REV input is synchronized to the clock or not. If both SR and REV are active at the same time, the storage element gets a value of 0.Reverse inputF O R As shown in Figure 5, the upper registers in both the outputand three-state paths share a common clock. The OTCLK1 clock signal drives the CK clock inputs of the upper registers N on the output and three-state paths. Similarly, OTCLK2 E drives the CK inputs for the lower registers on the output and three-state paths. The upper and lower registers on the W input path have independent clock lines: ICLK1 and ICLK2. The OCE enable line controls the CE inputs of the upper D and lower registers on the output path. Similarly, TCE Econtrols the CE inputs for the register pair on the three-state path and ICE does the same for the register pair on the input path. The Set/Reset (SR) line entering the IOB controls all six registers, as is the Reverse (REV) line. In addition to the signal polarity controls described in IOB Overview, each storage element additionally supports the controls described in Table 5.S Table 5: Storage Element Options I Option Switch G FF/Latch N SYNC/ASYNC SSRHIGH/SRLOW Function Chooses between an edge-triggered flip-flop or a level-sensitive latch Determines whether the SR set/reset control is synchronous or asynchronous S Determines whether SR acts as p Set, which forces a the storage element to a logic 1 (SRHIGH) or a a Reset, which forces a logic 0 (SRLOW) r Specificity Independent for each storage element Independent for each storage element Independent for each storage element, except when using ODDR2. In the latter case, the selection for the upper element will apply to both elements. Independent for each storage element, except when using ODDR2, which uses two IOBs. In the ODDR2 case, selecting INIT0 for one IOBs applies to both elements within the IOB, although INIT1 could be selected for the elements in the other IOB.INIT1/INIT0t When Global Set/Reset (GSR) is asserted or after a configuration this option specifies the initial state of the storage element, either set (INIT1) or reset n (INIT0). By default, choosing SRLOW also selects INIT0; choosing SRHIGH also selects INIT1. 3 F P G A F1 w D 2 w S w 3P R O Double-Data-Rate Transmission D Double-Data-Rate (DDR) transmission describes the U technique of synchronizing signals to both the rising and C falling edges of the clock signal. Spartan-3E devices use T register pairs in all three IOB paths to perform DDRoperations.N The pair of storage elements on the IOB‘s Output path O (OFF1 and OFF2), used as registers, combine with a special multiplexer to form a DDR D-type flip-flop (ODDR2). T This primitive permits DDR transmission where output data bits are synchronized to both the rising and falling edges of R a clock. DDR operation requires two clock signals (usually E 50% duty cycle), one the inverted form of the other. C These signals trigger the two registers in alternating fashion, as shown in Figure 7. The Digital Clock Manager O (DCM) generates the two clock signals by mirroring an M incoming signal, and then shifting it 180 degrees. This approach ensures minimal skew between the two signals. M Alternatively, the inverter inside the IOB can be used to E invert the clock signal, thus only using one clock line and N both rising and falling edges of that clock line as the two D clocks for the DDR flip-flops. E D F O R N E W D E S I G N Register Cascade Feature SDCM 180? 0? FDDR D1 Q1 CLK1 DDR MUX D2 Q2 CLK2 QThe storage-element pair on the Three-State path (TFF1 and TFF2) also can be combined with a local multiplexer to form a DDR primitive. This permits synchronizing the output enable to both the rising and falling edges of a clock. This DDR operation is realized in the same way as for the output path. The storage-element pair on the input path (IFF1 and IFF2) allows an I/O to receive a DDR signal. An incoming DDR clock signal triggers one register, and the inverted clock signal triggers the other register. The registers take turns capturing bits of the incoming DDR data signal. The primitive to allow this functionality is called IDDR2. Aside from high bandwidth data transfers, DDR outputs also can be used to reproduce, or mirror, a clock signal on the output. This approach is used to transmit clock and data signals together (source synchronously). A similar approach is used to reproduce a clock signal at multiple outputs. The advantage for both approaches is that skew across the outputs is minimal.DCM 0? FDDR D1 Q1 CLK1 DDR MUX D2 Q2 CLK2 QDS312-2_20_021105Figure 7: Two Methods for Clocking the DDR RegisterIDDR2As a DDR input pair, the master IOB registers incoming data on the rising edge of ICLK1 (= D1) and the rising edge of ICLK2 (= D2), which is typically the same as the falling edge of ICLK1. This data is then transferred into the FPGA fabric. At some point, both signals must be brought into the same clock domain, typically ICLK1. This can be difficult at high frequencies because the available time is only one half of a clock cycle assuming a 50% duty cycle. See Figure 8 for a graphical illustration of this function.In the Spartan-3E family, one of the IOBs in a differential S pair can cascade its input storage elements with those in p the other IOB as part of a differential pair. This is intended to a make DDR operation at high speed much simpler to r implement. The new DDR connections that are available t are shown in Figure 5 (dashed lines), and are only available a for routing between IOBs and are not accessible ton the FPGA fabric. Note that this feature is only available-when 3 using the differential I/O standards LVDS, RSDS, and MINI_LVDS. F P G A1 w D 3 w S w 3FP R O D U C T N O TD PAD QQD1 To FabricDD2ICLK2 ICLK1and the rising edge of OCLK2 (= D2), which is typically the same as the falling edge of OCLK1. These two bits of data are multiplexed by the DDR mux and forwarded to the output pin. The D2 data signal must be re-synchronized from the OCLK1 clock domain to the OCLK2 domain using FPGA slice flip-flops. Placement is critical at high frequencies, because the time available is only one half a clock cycle. See Figure 10 for a graphical illustration of this function. The C0 or C1 alignment feature of the ODDR2 flip-flop, originally introduced in the Spartan-3E FPGA family, is not recommended or supported in the ISE development software. The ODDR2 flip-flop without the alignment feature remains fully supported. Without the alignment feature, the ODDR2 feature behaves equivalent to the ODDR flip-flop on previous Xilinx FPGA families.R ICLK1 E C ICLK2 O PAD d d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8 M D1 d d+2 d+4 M d+6 d+8 E D2 d-1 d+1 d+3 d+5 N d+7 D E Figure 8: Input DDR (without Cascade Feature) D In the Spartan-3E device, the signal D2 can be cascadedD1 From Fabric D2DQ PADDS312-2_21_021105DQinto the storage element of the adjacent slave IOB. There it F is re-registered to ICLK1, and only then fed to the FPGA fabric where it is now already in the same time domain as O D1. Here, the FPGA fabric uses only the clock ICLK1 to R process the received data. See Figure 9 for a graphical illustration of this function.OCLK1 OCLK2N E W D E S I G N SPAD DOCLK1 D Q D1 OCLK2 D1 D2 D Q D2 PAD d d+1 d d+1 d+2 d+3 d+2 d+3 d+4 d+5 d+4 d+5 d+6 d+8 d+7 d+6 d+10 d+9 d+7 d+8To Fabric Q IQ2 IDDRIN2DS312-2_23_030105ICLK1 ICLK2Figure 10: Output DDRSelectIO Signal StandardsThe Spartan-3E I/Os feature inputs and outputs that support a wide range of I/O signaling standards (Table 6 and Table 7). The majority of the I/Os also can be used to form differential pairs to support any of the differential signaling standards (Table 7).ICLK 1 ICLK 2 PAD D1 D2 dS p a r d+1 d+2 d+3 d+4 d+5 d+6 d+7 d+8 t a n d+8 d d+2 d+4 d+6 d-1 d+1 d+3 d+5 3 d+7DS312-2_22_030105As a DDR output pair, the master IOB registers data coming from the FPGA fabric on the rising edge of OCLK1 (= D1)F Figure 9: Input DDR Using Spartan-3E Cascade Feature P G ODDR2 A1 w D 4 w S w 3FP To define the I/O signaling standard in a design, set R the IOSTANDARD attribute to the appropriate setting. Xilinx O provides a variety of different methods for applying the IOSTANDARD for maximum flexibility. For a full description D of different methods of applying attributes to control U IOSTANDARD, refer to the Xilinx Software Manuals and C Help. T N O T R E C O M M E N D E D F O R N E W D E S I G N SS p a r t a n 31 w D 5 w S w 3 . 1F P GP R O Spartan-3E FPGAs provide additional input flexibility by D allowing I/O standards to be mixed in different banks. For a U particular VCCO voltage, Table 6 and Table 7 list all of the C Table 6: Single-Ended IOSTANDARD Bank Compatibility TSingle-Ended N IOSTANDARDIOSTANDARDs that can be combined and if the IOSTANDARD is supported as an input only or can be used for both inputs and outputs.VCCO Supply/Compatibility 1.8V 2.5V 3.3V Input/ Output Input/ Output Input Input Input Input Input/ Output Input/ Output Input Input Input InputO T LVTTLLVCMOS33 R E LVCMOS25 C O LVCMOS18 M M LVCMOS15 E LVCMOS12 N D PCI33_3 E D PCI66_3 HSTL_I_18 F O HSTL_III_18 R1.2V1.5VInput/ Output -Input/ Output Input -Input/ Output Input Input Input/ Output Input/ Output Input/ Output -Input/ Output Input Input Input Input Input Input Input/ OutputN E W D E S I G N S1.SSTL18_I SSTL2_INotes: Input RequirementsN/R - Not required for input operation.VREF N/R(1) N/R N/R N/R N/R N/R N/R N/R 0.9Board Termination Voltage (VTT) N/R N/R N/R N/R N/R N/R N/R N/R 0.9 1.8S p a r t a n 3 F P G A F1 w D 6 w S w 31.1P R O Input D Table 7: Differential IOSTANDARD Bank Compatibility Differential Bank Requirements: VCCO Supply Restriction(1) U Differential VREF 1.8V 2.5V C IOSTANDARD Applies to Outputs Input, T OnlyLVDS_25 Input3.3V InputN RSDS_25 O TMINI_LVDS_25 VREF is not used for R LVPECL_25 these I/O standardsE Input, BLVDS_25 Input Input Output C No Differential Bank Restriction Input, O DIFF_HSTL_I_18 Input Input (other I/O bank Output M restrictions might Input, DIFF_HSTL_III_18 Input Input apply) M Output Input, E DIFF_SSTL18_I Input Input Output N Input, DIFF_SSTL2_I Input Input D Output E Notes: D Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs. 1.On-Chip Differential TerminationSpartan-3E devices provide an on-chip ~120Ω differential termination across the input differential receiver terminals. The on-chip input differential termination in Spartan-3E devices potentially eliminates the external 100Ω termination resistor commonly found in differential receiver circuits. Differential termination is used for LVDS, mini-LVDS, and RSDS as applications permit. On-chip Differential Termination is available in banks with VCCO = 2.5V and is not supported on dedicated input pins. Set the DIFF_TERM attribute to TRUE to enable Differential Termination on a differential I/O pin pair. The DIFF_TERM attribute uses the following syntax in the UCF file:INST &I/O_BUFFER_INSTANTIATION_NAME& DIFF_TERM = &&TRUE/FALSE&&;On-chip Differential Termination, Output Applies to Outputs Input, Only Input On-chip Differential Termination, Output Applies to Outputs Input, Only Input On-chip Differential Termination, Output Input InputInputInput InputHSTL and SSTL inputs use the Reference Voltage (VREF) to F bias the input-switching threshold. Once a configuration O data file is loaded into the FPGA that calls for the I/Os of a given bank to use HSTL/SSTL, a few specifically reserved R I/O pins on the same bank automatically convert to VREF inputs. For banks that do not contain HSTL or SSTL, VREF N pins remain available for user I/Os or input pins. Differential standards employ a pair of signals, one the W opposite polarity of the other. The noise canceling properties (for example, Common-Mode Rejection) of these standards permit exceptionally high data transfer rates. This D subsection introduces the differential signaling capabilities E of Spartan-3E devices. Each device-package combination designates specific I/O I pairs specially optimized to support differential standards. A G unique L-number, part of the pin name, identifies the line-pairs associated with each bank (see Module 4, Pinout N Descriptions). For each pair, the letters P and N designate S the true and inverted lines, respectively. For example, the S pin names IO_L43P_3 and IO_L43N_3 indicate the true p and inverted lines comprising the line pair L43 on Bank 3. a r VCCO provides current to the outputs and additionally t powers the On-Chip Differential Termination. VCCO must be a 2.5V when using the On-Chip Differential Termination. The n VREF lines are not required for differential operation. To further understand how to combine multiple 3 IOSTANDARDs within a bank, refer to IOBs Organized into Banks, page 18. F P G A1 w D 7 w S w 3ESFP R O D U Spartan-3E Differential C Output T N O T Spartan-3E DifferentialOutputZ0 = 50ΩSpartan-3E Differential InputPull-upOutput Path Z0 = 50Ω Spartan-3E Differential Input with On-Chip Differential Terminator Input PathR E C O Figure 11: Differential Inputs and Outputs M Pull-Up and Pull-Down Resistors M Pull-up and pull-down resistors inside each IOB optionally E force a floating I/O or Input-only pin to a determined state. N Pull-up and pull-down resistors are commonly applied to D unused I/Os, inputs, and three-state outputs, but can be used on any I/O or Input-only pin. The pull-up resistor E connects an IOB to VCCO through a resistor. The resistance DDS312-2_24_082605~ Z0 = 50Ω 1 2 0 Ω Z0 = 50Ω1 Keeper 0 0 ΩPull-downDS312-2_25_020807Figure 12: KeeperCircuitSlew Rate Control and Drive StrengthEach IOB has a slew-rate control that sets the output switching edge-rate for LVCMOS and LVTTL outputs. The SLEW attribute controls the slew rate and can either be set to SLOW (default) or FAST. Each LVCMOS and LVTTL output additionally supports up to six different drive current strengths as shown in Table 8. To adjust the drive strength for each output, the DRIVE attribute is set to the desired drive strength: 2, 4, 6, 8, 12, and 16. Unless otherwise specified in the FPGA application, the software default IOSTANDARD is LVCMOS25, SLOW slew rate, and 12 mA output drive. Table 8: Programmable Output Drive CurrentIOSTANDARD LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 Output Drive Current (mA) 2 ? ? ? ? ? ? 4 ? ? ? ? ? 6 ? ? ? ? ? 8 ? ? ? ? 12 ? ? ? 16 ? ? -value depends on the VCCO voltage (see Module 3, DC and Switching Characteristics for the specifications). The F pull-down resistor similarly connects an IOB to ground with a resistor. The PULLUP and PULLDOWN attributes and O library primitives turn on these optional resistors. R By default, PULLDOWN resistors terminate all unused I/O and Input-only pins. Unused I/O and Input-only pins can N alternatively be set to PULLUP or FLOAT. To change the E unused I/O Pad setting, set the Bitstream Generator (BitGen) option UnusedPin to PULLUP, PULLDOWN, or W FLOAT. The UnusedPin option is accessed through the Properties for Generate Programming File in ISE. See D Bitstream Generator (BitGen) Options. During configuration a Low logic level on the HSWAP pin S activates pull-up resistors on all I/O and Input-only pins not I actively used in the selected configuration mode.EKeeper Circuit NGS Each I/O has an optional keeper circuit (see Figure 12) that S keeps bus lines from floating when not being actively driven. p The KEEPER circuit retains the last logic level on a line after a all drivers have been turned off. Apply the KEEPER r attribute or use the KEEPER library primitive to use the t KEEPER circuitry. Pull-up and pull-down resistors override a the KEEPER settings. n 3F P G A FHigh output current drive strength and FAST output slew rates generally result in fastest I/O performance. However, these same settings generally also result in transmission line effects on the printed circuit board (PCB) for all but the shortest board traces. Each IOB has independent slew rate and drive strength controls. Use the slowest slew rate and lowest output drive current that meets the performance requirements for the end application. Likewise, due to lead inductance, a given package supports a limited number of simultaneous switching outputs (SSOs) when using fast, high-drive outputs. Only use fast, high-drive outputs when required by the application.1 w D 8 w S w 3P R O IOBs Organized into Banks D U The Spartan-3E architecture organizes IOBs into four I/O banks as shown in Figure 13. Each bank maintains C separate VCCO and VREF supplies. The separate supplies T allow each bank to independently set V . Similarly, theCCO1. All VREF pins must be connected within a bank. 2. 3. All VREF lines associated with the bank must be set to the same voltage level. The VREF levels used by all standards assigned to the Inputs of the bank must agree. The Xilinx development software checks for this. Table 6 describes how different standards use the VREF supply.VREF supplies can be set for each bank. Refer to Table 6 and Table 7 for VCCO and VREF requirements. NO When working with Spartan-3E devices, most of the T differential I/O standards are compatible and can becombined within any given bank. Each bank can support any two of the following differential standards: LVDS_25 R outputs, MINI_LVDS_25 outputs, and RSDS_25 outputs. As E an example, LVDS_25 outputs, RSDS_25 outputs, and any other differential inputs while using on-chip differential C termination are a valid combination. A combination not O allowed is a single bank with LVDS_25 outputs, RSDS_25 M outputs, and MINI_LVDS_25 outputs.If VREF is not required to bias the input switching thresholds, all associated VREF pins within the bank can be used as user I/Os or input pins.Package Footprint CompatibilitySometimes, applications outgrow the logic capacity of a specific Spartan-3E FPGA. Fortunately, the Spartan-3E family is designed so that multiple part types are available in pin-compatible package footprints, as described in Module 4, Pinout Descriptions. In some cases, there are subtle differences between devices available in the same footprint. These differences are outlined for each package, such as pins that are unconnected on one device but connected on another in the same package or pins that are dedicated inputs on one package but full I/O on another. When designing the printed circuit board (PCB), plan for potential future upgrades and package migration. The Spartan-3E family is not pin-compatible with any previous Xilinx FPGA family.M E B N a D n k E 1 3 D F O R NBank 0Bank 2DS312-2_26_021205Dedicated InputsDedicated Inputs are IOBs used only as inputs. Pin names designate a Dedicated Input if the name starts with IP, for example, IP or IP_Lxxx_x. Dedicated inputs retain the full functionality of the IOB for input functions with a single exception for differential inputs (IP_Lxxx_x). For the differential Dedicated Inputs, the on-chip differential termination is not available. To replace the on-chip differential termination, choose a differential pair that supports outputs (IO_Lxxx_x) or use an external 100Ω termination resistor on the board.Figure 13: Spartan-3E I/O Banks (top view)I/O Banking Rules EW When assigning I/Os to banks, these VCCO rules must be followed: D 1. All VCCO pins on the FPGA must be connected even if a E bank is unused. S 2. All VCCO lines associated within a bank must be set to I the same voltage level.3. The VCCO levels used by all standards assigned to the G N I/Os of any given bank must agree. The Xilinx development software checks for this. Table 6 and S Table 7 describe how different standards use the VCCO S supply. p 4. If a bank does not have any VCCO requirements, a connect VCCO to an available voltage, such as r 2.5V or 3.3V. Some configuration modes might place additional t VCCO requirements. Refer to Configuration for more a information. n If any of the standards assigned to the Inputs of the bank 3 use VREF, then the following additional rules must be observed: F P G A FESD ProtectionClamp diodes protect all device pads against damage from Electro-Static Discharge (ESD) as well as excessive voltage transients. Each I/O has two clamp diodes: one diode extends P-to-N from the pad to VCCO and a second diode extends N-to-P from the pad to GND. During operation, these diodes are normally biased in the off state. These clamp diodes are always connected to the pad, regardless of the signal standard selected. The presence of diodes limits the ability of Spartan-3E I/Os to tolerate high signal voltages. The VIN absolute maximum rating in Table 73 of Module 3, DC and Switching Characteristics specifies the voltage range that I/Os can tolerate.1 w D 9 w S w 3P R O Supply Voltages for the IOBs D The IOBs are powered by three supplies: U C 1. The VCCO supplies, one for each of the FPGA‘s I/O T banks, power the output drivers. The voltage on the N 2. O T 3.VCCO pins determines the voltage swing of the output signal. VCCINT is the main power supply for the FPGA‘s internal logic. VCCAUX is an auxiliary source of power, primarily to optimize the performance of various FPGA functions such as I/O switching.beginning of design operation in the User mode. After the GTS net is released, all user I/Os go active while all unused I/Os are pulled down (PULLDOWN). The designer can control how the unused I/Os are terminated after GTS is released by setting the Bitstream Generator (BitGen) option UnusedPin to PULLUP, PULLDOWN, or FLOAT. One clock cycle later (default), the Global Write Enable (GWE) net is released allowing the RAM and registers to change states. Once in User mode, any pull-up resistors enabled by HSWAP revert to the user settings and HSWAP is available as a general-purpose I/O. For more information on PULLUP and PULLDOWN, see Pull-Up and Pull-Down Resistors.R E I/O and Input-Only Pin Behavior During C Power-On, Configuration, and User Mode O In this section, all behavior described for I/O pins also M applies to input-only pins and dual-purpose I/O pins that are M not actively involved in the currently-selected configuration E mode. N All I/O pins have ESD clamp diodes to their respective VCCO D supply and from GND, as shown in Figure 5. The VCCINT E (1.2V), VCCAUX (2.5V), and VCCO supplies can be applied in any order. Before the FPGA can start its configuration Dprocess, VCCINT, VCCO Bank 2, and VCCAUX must have reached their respective minimum recommended operating F levels indicated in Table 74. At this time, all output drivers O are in a high-impedance state. VCCO Bank 2, VCCINT, and VCCAUX serve as inputs to the internal Power-On Reset R circuit (POR). A Low level applied to the HSWAP input enables pull-up N resistors on user-I/O and input-only pins from power-on E throughout configuration. A High level on HSWAP disables W the pull-up resistors, allowing the I/Os to float. HSWAP contains an internal pull-up resistor and defaults to High if left floating. As soon as power is applied, the FPGA begins D initializing its configuration memory. At the same time, the E FPGA internally asserts the Global Set-Reset (GSR), which S asynchronously resets all IOB storage elements to a default Low state. Also see Pin Behavior During Configuration. IBehavior of Unused I/O Pins After ConfigurationBy default, the Xilinx ISE development software automatically configures all unused I/O pins as input pins with individual internal pull-down resistors to GND. This default behavior is controlled by the UnusedPin bitstream generator (BitGen) option, as described in Table 69.JTAG Boundary-Scan CapabilityAll Spartan-3E IOBs support boundary-scan testing compatible with IEEE 2 standards. During boundary-scan operations such as EXTEST and HIGHZ the pull-down resistor is active. See JTAG Mode for more information on programming via JTAG.G Upon the completion of initialization and the beginning of configuration, INIT_B goes High, sampling the M0, M1, and N M2 inputs to determine the configuration mode. S Configuration data is then loaded into the FPGA. The I/O S drivers remain in a high-impedance state (with or without p pull-up resistors, as determined by the HSWAP input) a throughout configuration. rAt the end of configuration, the GSR net is released,tplacing a the IOB registers in a Low state by default, unless the n loaded design reverses the polarity of their respective SR inputs. 3 The Global Three State (GTS) net is released during Start-Up, marking the end of configuration and the F P G A2 w D 0 w S w 3FP R O Configurable Logic Block (CLB) and D Slice Resources U C For additional information, refer to the DUsing Configurable T Logic Blocks (CLBs)‖ chapter in UG331.CLB Overview(SRL16), and additional multiplexers and carry logic simplify wide logic and arithmetic functions. Most general-purpose logic in a design is automatically mapped to the slice resources in the CLBs. Each CLB is identical, and the Spartan-3E family CLB structure is identical to that for the Spartan-3 family.NThe Configurable Logic Blocks (CLBs) constitute the main O logic resource for implementing synchronous as well as T combinatorial circuits. Each CLB contains four slices, and each slice contains two Look-Up Tables (LUTs) to implement logic and two dedicated storage elements that R can be used as flip-flops or latches. The LUTs can be used E as a 16x1 memory (RAM16) or as a 16-bit shift registerCLB ArrayThe CLBs are arranged in a regular array of rows and columns as shown in Figure 14. Each density varies by the number of rows and columns of CLBs (see Table 9).C O M M E N D E FPGA D Spartan-3EX2Y3 X3Y3 X0Y3 X1Y3 F X0Y2 O R X0Y1X1Y2 X2Y2 X3Y2IOBsX1Y1X2Y1X3Y1CLBSliceDS312-2_31_021205X0Y0 N X1Y0 X2Y0 X3Y0 Table 9: Spartan-3E CLB Resources E W Device CLB CLBFigure 14: CLB LocationsRowsColumnsCLB Total(1)SlicesLUTs / Flip-FlopsEquivalent Logic CellsRAM16 / SRL16Distributed RAM BitsXC3S100E 22 16 240 960 1,920 2,160 960 15,360 D XC3S250E 34 26 612 2,448 4,896 5,508 2,448 39,168 E XC3S500E 46 34 1,164 4,656 9,312 10,476 4,656 74,496 S 60 46 2,168 8,672 17,344 19,512 8,672 138,752 IXC3S1200E XC3S 3,688 14,752 29,504 33,192 14,752 236,032 G N Notes: S The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are 1.S p a Slices r Each CLB comprises four interconnected slices, ast shown in Figure 16. These slices are grouped in pairs. Each pair is a organized as a column with an independent carry chain. n The left pair supports both logic and memory functions and 3 its slices are called SLICEM. The right pair supports logic only and its slices are called SLICEL. Therefore half the F P G A2 w D 1 w S w 3embedded in the array (see Figure 1 in Module 1).LUTs support both logic and memory (including both RAM16 and SRL16 shift registers) while half support logic only, and the two types alternate throughout the array columns. The SLICEL reduces the size of the CLB and lowers the cost of the device, and can also provide a performance advantage over the SLICEM.FP R O D U C T N O T R E C O M M E N D E D F O R N E W D E S I G N S.WSDIDI DWF[4:1]S p a r t DS312-2_32_042007 a Notes: n 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can be 6, 7, or 8, depending on the slice. The upper SLICEL has an F8MUX, and the upper SLICEM has 3an F7MUX. The lower SLICEL and SLICEM both have an F6MUX.2 w D 2 w S w 3F Figure 15: Simplified Diagram of the Left-Hand SLICEM P G A FP R O D U C T N O TSwitch R Matrix E C O SHIFTOUT SHIFTIN SLICE M X0Y1 M E N D E Slice Location Designations DLeft-Hand SLICEM (Logic or Distributed RAM or Shift Register)Right-Hand SLICEL (Logic Only) COUTCLB SLICE X1Y1SLICE X1Y0 COUT CIN Interco nnect to NeighborsSLICE X0Y0CINDS099-2_05_082104Figure 16: Arrangement of Slices within the CLBSlice OverviewA slice includes two LUT function generators and two storage elements, along with additional logic, as shown in Figure 17. Both SLICEM and SLICEL have the following elements in common to provide logic, arithmetic, and ROM functions: ? ? ? ? Two 4-input LUT function generators, F and G Two storage elements Two wide-function multiplexers, F5MUX and FiMUX Carry and arithmetic logicThe Xilinx development software designates the location of a slice according to its X and Y coordinates, starting in the F bottom left corner, as shown in Figure 14. The letter ?X‘ O followed by a number identifies columns of slices, incrementing from the left side of the die to the right. The R letter ?Y‘ followed by a number identifies the position of each slice in a pair as well as indicating the CLB row, N incrementing from the bottom of the die. Figure 16 shows the CLB located in the lower left-hand corner of the die. The E SLICEM always has an even ?X‘ number, and the SLICEL W always has an odd ?X‘ number.D E S I G N SSRL16 RAM16 LUT4 (G)FiMUX Carry RegisterLUT4 (G)FiMUX Carry RegisterSRL16 RAM16 LUT4 (F)SLICEMS p a Carry Register r t a Arithmetic Logic n 3F5MUXF5MUX CarryLUT4 (F) Arithmetic LogicDS312-2_13_020905RegisterSLICEL2 w D 3 w S w 3Figure 17: Resources in a Slice F P G A FP R O The SLICEM pair supports two additional functions: D ? Two 16x1 distributed RAM blocks, RAM16 U ? Two 16-bit shift registers, SRL16 C Each of these elements is described in more detail in the Tfollowing sections.Enable (CE), Slice Write Enable (SLICEWE1), and Reset/Set (RS) are shared in common between the two halves. The LUTs located in the top and bottom portions of the slice are referred to as DG‖ and DF‖, respectively, or the DG-LUT‖ and the DF-LUT‖. The storage elements in the top and bottom portions of the slice are called FFY and FFX, respectively. Each slice has two multiplexers with F5MUX in the bottom portion of the slice and FiMUX in the top portion. Depending on the slice, the FiMUX takes on the name F6MUX, F7MUX, or F8MUX, according to its position in the multiplexer chain. The lower SLICEL and SLICEM both have an F6MUX. The upper SLICEM has an F7MUX, and the upper SLICEL has an F8MUX. The carry chain enters the bottom of the slice as CIN and exits at the top as COUT. Five multiplexers control the chain: CYINIT, CY0F, and CYMUXF in the bottom portion and CY0G and CYMUXG in the top portion. The dedicated arithmetic logic includes the exclusive-OR gates XORF and XORG (bottom and top portions of the slice, respectively) as well as the AND gates FAND and GAND (bottom and top portions, respectively). See Table 10 for a description of all the slice input and output signals.N O The combination of a LUT and a storage element is known TLogic Cellsas a DLogic Cell‖. The additional features in a slice, such as the wide multiplexers, carry logic, and arithmetic gates, add R to the capacity of a slice, implementing logic that would otherwise require additional LUTs. Benchmarks have E shown that the overall slice is equivalent to 2.25 simple logic C cells. This calculation provides the equivalent logic cell O count shown in Table 9.M Slice Details M E Figure 15 is a detailed diagram of the SLICEM. It represents N a superset of the elements and connections to be found in all slices. The dashed and gray lines (blue when viewed in D color) indicate the resources found only in the SLICEM and E not in the SLICEL. DEach slice has two halves, which are differentiated as top and bottom to keep them distinct from the upper and lower F slices in a CLB. The control inputs for the clock (CLK), Clock Table 10: Slice Inputs and OutputsName Location SLICEL/M Bottom SLICEL/M Top SLICEL/M Bottom SLICEL/M Top SLICEM Bottom SLICEM Top SLICEM Top SLICEM Top SLICEM Common SLICEL/M Bottom SLICEL/M Top SLICEL/M Top SLICEL/M Top SLICEL/M Common SLICEL/M Common SLICEL/M Common SLICEM Top Direction Input Input Input Input Output Output Input Output Input Output Input Input Output Input Input Input InputO RDescription F-LUT and FAND inputs G-LUT and GAND inputs or Write Address (SLICEM) Bypass to or output (SLICEM) or storage element, or control input to F5MUX, input to carry logic, or data input to RAM (SLICEM) Bypass to or output (SLICEM) or storage element, or control input to FiMUX, input to carry logic, or data input to RAM (SLICEM) BX bypass output BY bypass output Alternate data input to RAM ALTDIG or SHIFTIN bypass output RAM Write EnableF[4:1] N G[4:1] E BX WD E BXOUT S BYOUT IALTDIG G DIG N SLICEWE1 S F5FXINA FXINB Fi CE SR CLK SHIFTINBYS p Input to FiMUX; direct feedback from F5MUX or another FiMUX a Input to FiMUX; direct feedback from F5MUX or another FiMUX r t Output from FiMUX; direct feedback to another FiMUX a FFX/Y Clock Enable n FFX/Y Set or Reset or RAM Write Enable (SLICEM) 3 FFX/Y Clock or RAM Clock (SLICEM)Data input to G-LUT RAMOutput from F5MUX; direct feedback to FiMUX2 w D 4 w S w 3F P G A FP R O Table 10: Slice Inputs and Outputs (Cont’d) D Location Direction U Name SHIFTOUT SLICEM Bottom Output C CIN SLICEL/M Bottom Input TCOUT X N Y O XB T YB SLICEL/M Top SLICEL/M Bottom SLICEL/M Top SLICEL/M Bottom SLICEL/M Top Output Output Output Output OutputDescription Shift data output from F-LUT RAM Carry chain input Carry chain output Combinatorial output Combinatorial output Combinatorial output from carry or F-LUT SRL16 (SLICEM) Combinatorial output from carry or G-LUT SRL16 (SLICEM)R XQ SLICEL/M Bottom Output FFX output E YQ SLICEL/M Top Output FFY output C Main Logic Paths O M Central to the operation of each slice are two nearly M identical data paths at the top and bottom of the slice. The description that follows uses names associated with the E bottom path. (The top path names appear in parentheses.) N The basic path originates at an interconnect switch matrix D outside the CLB. See Interconne